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P89LPC9351FDH,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P74
P89LPC9351_1 © NXP B.V. 2008. All rights reserved.
Preliminary data sheet Rev. 01 — 19 November 2008 49 of 74
NXP Semiconductors
P89LPC9351
8-bit microcontroller with 8-bit ADC
7.30.8 ISP
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal firmware to
facilitate remote programming of the P89LPC9351 through the serial port. This firmware is
provided by NXP and embedded within each P89LPC9351 device. The NXP ISP facility
has made in-system programming in an embedded application possible with a minimum
of additional expense in components and circuit board area. The ISP function uses five
pins (V
DD
, V
SS
, TXD, RXD, and RST). Only a small connector needs to be available to
interface your application to an external circuit in order to use this feature.
7.30.9 Power-on reset code execution
The P89LPC9351 contains two special flash elements: the Boot Vector and the Boot
Status bit. Following reset, the P89LPC9351 examines the contents of the Boot Status bit.
If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which is
the normal start address of the user’s application code. When the Boot Status bit is set to
a value other than zero, the contents of the Boot Vector are used as the high byte of the
execution address and the low byte is set to 00H.
Table 8 shows the factory default Boot Vector setting for these devices. A factory-provided
bootloader is pre-programmed into the address space indicated and uses the indicated
bootloader entry point to perform ISP functions. This code can be erased by the user.
Remark: Users who wish to use this loader should take precautions to avoid erasing the
1 kB sector that contains this bootloader. Instead, the page erase function can be used to
erase the first eight 64-byte pages located in this sector.
A custom bootloader can be written with the Boot Vector set to the custom bootloader, if
desired.
7.30.10 Hardware activation of the bootloader
The bootloader can also be executed by forcing the device into ISP mode during a
power-on sequence (see the P89LPC9351
User manual
for specific information). This has
the same effect as having a non-zero status byte. This allows an application to be built that
will normally execute user code but can be manually forced into ISP operation. If the
factory default setting for the boot vector (1FH) is changed, it will no longer point to the
factory pre-programmed ISP bootloader code. After programming the flash, the status
byte should be programmed to zero in order to allow execution of the user’s application
code beginning at address 0000H.
7.31 User configuration bytes
Some user-configurable features of the P89LPC9351 must be defined at power-up and
therefore cannot be set by the program after start of execution. These features are
configured through the use of the flash byte UCFG1 and UCFG2. Please see the
P89LPC9351
User’s Manual
for additional details.
Table 8. Default boot vector values and ISP entry points
Device Default
boot vector
Default
bootloader
entry point
Default bootloader
code range
1 kB sector
range
P89LPC9351 1FH 1F00H 1E00H to 1FFFH 1C00H to 1FFFH
P89LPC9351_1 © NXP B.V. 2008. All rights reserved.
Preliminary data sheet Rev. 01 — 19 November 2008 50 of 74
NXP Semiconductors
P89LPC9351
8-bit microcontroller with 8-bit ADC
7.32 User sector security bytes
There are eight User Sector Security Bytes on the P89LPC9351. Each byte corresponds
to one sector. Please see the P89LPC9351
User manual
for additional details.
8. ADC
8.1 General description
The P89LPC9351 has two 8-bit, 4-channel multiplexed successive approximation
analog-to-digital converter modules. Two high-speed programmable gain amplifiers (PGA)
are integrated. The PGAs provide selectable gains of 2x, 4x, 8x, or 16x. An on-chip
temperature sensor is integrated within one of the ADC and operates over wide
temperature. A block diagram of the ADC is shown in Figure 20 “ADC block diagram”.
Both ADCs consist of an 4-input multiplexer which feeds a sample-and-hold circuit
providing an input signal to comparator inputs. The control logic in combination with the
SAR drives a digital-to-analog converter which provides the other input to the comparator.
The output of the comparator is fed to the SAR.
8.2 Features
n Two 8-bit, 4-channel multiplexed input, successive approximation ADCs.
n Programmable Gain Amplifier (PGA) with selectable gains of 2x, 4x, 8x, or 16x.
n On-chip wide range temperature sensor.
n Four result registers for each A/D.
n Six operating modes:
u Fixed channel, single conversion mode.
u Fixed channel, continuous conversion mode.
u Auto scan, single conversion mode.
u Auto scan, continuous conversion mode.
u Dual channel, continuous conversion mode.
u Single step mode.
n Four conversion start modes:
u Timer triggered start.
u Start immediately.
u Edge triggered.
u Dual start immediately.
n 8-bit conversion time of ≥1.61 µs at an A/D clock of 8.0 MHz.
n Interrupt or polled operation.
n Boundary limits interrupt.
n DAC output to a port pin with high output impedance.
n Clock divider.
n Power-down mode.
P89LPC9351_1 © NXP B.V. 2008. All rights reserved.
Preliminary data sheet Rev. 01 — 19 November 2008 51 of 74
NXP Semiconductors
P89LPC9351
8-bit microcontroller with 8-bit ADC
8.3 Block diagram
8.4 PGA
Additional PGA module is integrated in each ADC module to improve the effective
resolution of the ADC. A single channel can be selected for amplification. The gain of PGA
can be programmable to 2, 4, 8 and 16. Please refer to Table 10 “Static characteristics” for
detailed specifications.
Register PGACONx and PGACONxB are used to for PGA configuration. Register
PGAxTRIM2X4X and PGAxTRIM8X16X provide trim value of PGA gain level. As
power-on, default trim value for each gain setting is loaded into the PGA trim registers. For
accurate measurements, offset calibration is required.
Please see the P89LPC9351
User manual
for detail configuration, calibration, and usage
information.
8.5 Temperature sensor
An on-chip wide-temperature range temperature sensor is integrated with ADC0 module.
It provides temperature sensing capability of −40 °C ~ 85 °C. It is necessary to measure
the 1.2 V reference voltage via the ADC before measuring temperature. The reference
voltage, temperature sensor and AD03 input pin multiplex one input to PGA0. Please see
the P89LPC9351
User manual
for detail usage of temperature sensor.
Fig 20. ADC block diagram
+
–
comp
PGA0
AD00
8
CONTROL
LOGIC
AD01
AD02
AD03
V
ref(bg)
V
sen
+
–
comp
to comparators
SAR
SAR
8
input MUX
Anin00
Anin01
Anin02
Anin03
input MUX
CCLK
002aad576
PGA1
AD10
4
AD11
AD12
AD13
DAC0
DAC1
Anin10
Anin11
Anin12
Anin13
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P74

P89LPC9351FDH,518

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Buy P89LPC9351FDH,518
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU Enhanced LPC935
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New from this manufacturer.
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