P89LPC9351_1 © NXP B.V. 2008. All rights reserved.
Preliminary data sheet Rev. 01 — 19 November 2008 61 of 74
NXP Semiconductors
P89LPC9351
8-bit microcontroller with 8-bit ADC
Table 12. Dynamic characteristics (18 MHz)
V
DD
= 3.0 V to 3.6 V unless otherwise specified.
T
amb
=
40
°
C to +85
°
C for industrial applications, unless otherwise specified.
[1][2]
Symbol Parameter Conditions Variable clock f
osc
=18MHz Unit
Min Max Min Max
f
osc(RC)
internal RC oscillator
frequency
nominal f = 7.3728 MHz
trimmed to ± 1 % at
T
amb
=25°C; clock
doubler option = OFF
(default)
7.189 7.557 7.189 7.557 MHz
nominal f = 14.7456 MHz;
clock doubler option = ON
14.378 15.114 14.378 15.114 MHz
f
osc(WD)
internal watchdog
oscillator frequency
T
amb
=25°C 380 420 380 420 kHz
f
osc
oscillator frequency 0 18 - - MHz
T
cy(clk)
clock cycle time see Figure 22 55 - - - ns
f
CLKLP
low-power select clock
frequency
0 8 - - MHz
Glitch filter
t
gr
glitch rejection time P1.5/RST pin - 50 - 50 ns
any pin except P1.5/
RST - 15 - 15 ns
t
sa
signal acceptance time P1.5/RST pin 125 - 125 - ns
any pin except P1.5/
RST 50 - 50 - ns
External clock
t
CHCX
clock HIGH time see Figure 22 22 T
cy(clk)
t
CLCX
22 - ns
t
CLCX
clock LOW time see Figure 22 22 T
cy(clk)
t
CHCX
22 - ns
t
CLCH
clock rise time see Figure 22 -5-5ns
t
CHCL
clock fall time see Figure 22 -5-5ns
Shift register (UART mode 0)
T
XLXL
serial port clock cycle
time
see Figure 21 16T
cy(clk)
- 888 - ns
t
QVXH
output data set-up to
clock rising edge time
see Figure 21 13T
cy(clk)
- 722 - ns
t
XHQX
output data hold after
clock rising edge time
see Figure 21 -T
cy(clk)
+ 20 - 75 ns
t
XHDX
input data hold after
clock rising edge time
see Figure 21 -0-0ns
t
XHDV
input data valid to clock
rising edge time
see Figure 21 150 - 150 - ns
SPI interface
f
SPI
SPI operating frequency
slave 0
CCLK
6
0 3.0 MHz
master -
CCLK
4
- 4.5 MHz
T
SPICYC
SPI cycle time see Figure 23, 24, 25, 26
slave
6
CCLK
- 333 - ns
master
4
CCLK
- 222 - ns
P89LPC9351_1 © NXP B.V. 2008. All rights reserved.
Preliminary data sheet Rev. 01 — 19 November 2008 62 of 74
NXP Semiconductors
P89LPC9351
8-bit microcontroller with 8-bit ADC
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
t
SPILEAD
SPI enable lead time see Figure 25, 26
slave 250 - 250 - ns
t
SPILAG
SPI enable lag time see Figure 25, 26
slave 250 - 250 - ns
t
SPICLKH
SPICLK HIGH time see Figure 23, 24, 25, 26
slave
3
CCLK
- 167 - ns
master
2
CCLK
- 111 - ns
t
SPICLKL
SPICLK LOW time see Figure 23, 24, 25, 26
slave
3
CCLK
- 167 - ns
master
2
CCLK
- 111 - ns
t
SPIDSU
SPI data set-up time see Figure 23, 24, 25, 26
master or slave 100 - 100 - ns
t
SPIDH
SPI data hold time see Figure 23, 24, 25, 26
master or slave 100 - 100 - ns
t
SPIA
SPI access time see Figure 25, 26
slave 0 80 0 80 ns
t
SPIDIS
SPI disable time see Figure 25, 26
slave 0 160 - 160 ns
t
SPIDV
SPI enable to output
data valid time
see Figure 23, 24, 25, 26
slave - 160 - 160 ns
master - 111 - 111 ns
t
SPIOH
SPI output data hold
time
see Figure 23, 24, 25, 26 0-0-ns
t
SPIR
SPI rise time see Figure 23, 24, 25, 26
SPI outputs (SPICLK,
MOSI, MISO)
- 100 - 100 ns
SPI inputs (SPICLK,
MOSI, MISO,
SS)
- 2000 - 2000 ns
t
SPIF
SPI fall time see Figure 23, 24, 25, 26
SPI outputs (SPICLK,
MOSI, MISO)
- 100 - 100 ns
SPI inputs (SPICLK,
MOSI, MISO,
SS)
- 2000 - 2000 ns
Table 12. Dynamic characteristics (18 MHz)
…continued
V
DD
= 3.0 V to 3.6 V unless otherwise specified.
T
amb
=
40
°
C to +85
°
C for industrial applications, unless otherwise specified.
[1][2]
Symbol Parameter Conditions Variable clock f
osc
=18MHz Unit
Min Max Min Max
P89LPC9351_1 © NXP B.V. 2008. All rights reserved.
Preliminary data sheet Rev. 01 — 19 November 2008 63 of 74
NXP Semiconductors
P89LPC9351
8-bit microcontroller with 8-bit ADC
11.1 Waveforms
Fig 21. Shift register mode timing
01234567
valid valid valid valid valid valid valid valid
T
XLXL
002aaa906
set TI
set RI
t
XHQX
t
QVXH
t
XHDV
t
XHDX
clock
output data
write to SBUF
input data
clear RI
Fig 22. External clock timing (with an amplitude of at least V
i(RMS)
= 200 mV)
t
CHCL
t
CLCX
t
CHCX
T
cy(clk)
t
CLCH
002aaa907
Fig 23. SPI master timing (CPHA = 0)
T
SPICYC
t
SPICLKH
t
SPICLKH
t
SPICLKL
t
SPICLKL
master LSB/MSB outmaster MSB/LSB out
t
SPIDH
t
SPIDSU
t
SPIF
t
SPIOH
t
SPIDV
t
SPIR
t
SPIDV
t
SPIF
t
SPIR
t
SPIF
t
SPIR
SS
SPICLK
(CPOL = 0)
(output)
002aaa908
SPICLK
(CPOL = 1)
(output)
MISO
(input)
MOSI
(output)
LSB/MSB in
MSB/LSB in

P89LPC9351FDH,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU Enhanced LPC935
Lifecycle:
New from this manufacturer.
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