P89LPC9351_1 © NXP B.V. 2008. All rights reserved.
Preliminary data sheet Rev. 01 — 19 November 2008 37 of 74
NXP Semiconductors
P89LPC9351
8-bit microcontroller with 8-bit ADC
7.23.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),
8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored
in RB8 in special function register SCON. The baud rate is variable and is determined by
the Timer 1 overflow rate or the baud rate generator (described in Section 7.23.5 “Baud
rate generator and selection”).
7.23.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data
bits (LSB first), a programmable 9
th
data bit, and a stop bit (logic 1). When data is
transmitted, the 9
th
data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.
Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is
received, the 9
th
data bit goes into RB8 in special function register SCON, while the stop
bit is not saved. The baud rate is programmable to either
1
⁄
16
or
1
⁄
32
of the CPU clock
frequency, as determined by the SMOD1 bit in PCON.
7.23.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8
data bits (LSB first), a programmable 9
th
data bit, and a stop bit (logic 1). In fact, Mode 3 is
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable
and is determined by the Timer 1 overflow rate or the baud rate generator (described in
Section 7.23.5 “Baud rate generator and selection”).
7.23.5 Baud rate generator and selection
The P89LPC9351 enhanced UART has an independent baud rate generator. The baud
rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs
which together form a 16-bit baud rate divisor value that works in a similar manner as
Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be
used for other timing functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 11). Note
that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent baud rate generators use OSCCLK.
7.23.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)
is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is
logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up
when SMOD0 is logic 0.
Fig 11. Baud rate sources for UART (Modes 1, 3)
baud rate modes 1 and 3
SBRGS = 1
SBRGS = 0
SMOD1 = 0
SMOD1 = 1
timer 1 overflow
(PCLK-based)
baud rate generator
(CCLK-based)
002aaa897
÷2
