P89LPC9351FDH,518

P89LPC9351_1 © NXP B.V. 2008. All rights reserved.

Preliminary data sheet Rev. 01 — 19 November 2008 52 of 74

8.6.1 Fixed channel, single conversion mode

selection. If PGA is enabled, all the selected channels for A/D conversion will be amplified

A single input channel can be selected for continuous conversion. The results of the

conversions will be sequentially placed in the four result register. The user may select

whether an interrupt can be generated after every four conversions. Additional conversion

results will again cycle through the four result register, overwriting the previous results.

conversion of each selected input will be performed and the result placed in the result

register which corresponds to the selected input channel. An interrupt, if enabled, will be

generated after all selected channels have been converted. If only a single channel is

selected this is equivalent to single channel, single conversion mode.

and the gain amplify level is the same.

8.6.4 Auto scan, continuous conversion mode

Any combination of the four input channels can be selected for conversion. A conversion

terminated by the user.

In auto scan mode, the PGA channel selection is dependent on the ADC channel

selection. If PGA is enabled, all the selected channel for A/D conversion will be amplified

and the gain amplify level is the same.

8.6.5 Dual channel, continuous conversion mode

on two user-selectable inputs. The result of the conversion of the first channel is placed in

the result register, ADxDAT0. The result of the conversion of the second channel is placed

in result register, ADxDAT1. The first channel is again converted and its result stored in

P89LPC9351_1 © NXP B.V. 2008. All rights reserved.

Preliminary data sheet Rev. 01 — 19 November 2008 53 of 74

ADxDAT2. The second channel is again converted and its result placed in ADxDAT3. An

interrupt is generated, if enabled, after every set of four conversions (two conversions per

channel).

combination of the four input channels can be selected for conversion. After each channel

is converted, an interrupt is generated, if enabled, and the A/D waits for the next start

condition. May be used with any of the start modes.

In Single step mode, the PGA channel selection is independent and can be different to

A/D conversion channel selection. If different, the gain of the selected ADC channel is 1.

triggered start mode is available in all ADC operating modes.

8.7.2 Start immediately

Programming this mode immediately starts a conversion. This start mode is available in all

ADC operating modes.

8.7.3 Edge triggered

An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has

started, additional edge triggers are ignored until the conversion has completed. The edge

triggered start mode is available in all ADC operating modes.

8.7.4 Dual start immediately

Programming this mode starts a synchronized conversion of both A/D converters. This

start mode is available in all A/D operating modes. Both A/D converters must be in the

same operating mode. In the continuous conversion modes, both A/D converters must

select an identical number of channels. Any trigger of either A/D will start a simultaneous

conversion of both A/Ds.

high and low registers. If the four MSBs of the conversion are outside the limit an interrupt

limits will again be compared after all 8 bits have been converted. An interrupt will be

P89LPC9351_1 © NXP B.V. 2008. All rights reserved.

Preliminary data sheet Rev. 01 — 19 November 2008 54 of 74

ADxDAT3), the DAC output will appear on the channel 3 pin.

The ADC requires that its internal clock source be in the range of 320 kHz to 8 MHz to