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ISL98003CNZ-165

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
10
FN6760.0
September 12, 2008
Register Listing
ADDRESS
REGISTER
(DEFAULT VALUE) BITS FUNCTION NAME DESCRIPTION
STATUS AND INTERRUPT REGISTERS
0x01 Selected Input Channel
Characteristics, (read only)
1:0 SYNC Type 00: Automatic Sync Selection logic could not find good sync on
H, V, or SOG (Automatic Sync mode only).
01: SYNC on HSYNC/VSYNC
10: CSYNC on HSYNC
11: CSYNC on Green Channel (SOG)
2 HSYNC Polarity 0: HSYNC Active High
1: HSYNC Active Low
3 VSYNC Polarity 0: VSYNC Active High
1: VSYNC Active Low
4 Tri-level Sync 0: Bi-level SOG (if SOG is active)
1: Tri-level SOG
5 Interlaced
(Only for CSYNC)
0: Non-interlaced or progressive signal
1: Interlaced signal
6 Macrovision 0: No Macrovision detected
1: Macrovision encoding detected
7 PLL Locked 0: PLL unlocked
1: PLL locked to incoming HSYNC
0x02 CH0 and CH1 Activity
Status, (read only)
0 HSYNC0 Activity 0: HSYNC0 Inactive
1: HSYNC0 Active – There is a periodic signal with frequency
>1kHz and consistent low/high times on this input.
1 VSYNC0 Activity 0: VSYNC0 Inactive
1: VSYNC0 Active – There is a periodic signal with frequency
>20Hz and consistent low/high times on this input.
3:2 SOG0 Activity 00: SOG0 Inactive – No transitions detected at the SOG Slicer
output.
01: SOG0 Active – Non-periodic transitions detected at the
SOG Slicer output – possibly valid SOG with a bad slicer
threshold, or simply video with no valid SOG.
10: SOG0 Periodic – There is a periodic signal with frequency
>1kHz and consistent low/high times on this input. This is
most likely a valid SOG signal.
4 HSYNC1 Activity See HSYNC0 Activity description
5 VSYNC1 Activity See VSYNC0 Activity description
7:6 SOG1 Activity See SOG0 Activity description
0x03 Not Used (read only) 7:0 Not Used Ignore
ISL98003
11
FN6760.0
September 12, 2008
0x04 Interrupt Status,
Write a 1 to each bit to clear
it, 0xFF to clear all.
0 CH0 Sync Changed 0: No change
1: CH0 activity or polarity changed
1 CH1 Sync Changed 0: No change
1: CH1 activity or polarity changed
2 N/A Ignore
3 N/A Ignore
4 Selected Input Channel
Disrupted
0: No change
1: Currently selected Input Channel’s HSYNC or VSYNC
signal has changed (fast notification of a mode change).
5 Selected Input Channel
Changed
0: No change
1: Currently selected Input Channel’s HSYNC or VSYNC
period or pulse width has settled to a new value and can be
measured.
6 VSYNC INT 0: Default state
1: VSYNC occurred
7 PADJ INT 0: Default state
1: Phase Adjustment function completed.
0x05 Interrupt Mask Register,
(0xFF)
0 CH0 Mask 0: Generate interrupt if CH0 sync activity, polarity, period, or
pulse width changes.
1: Mask CH0 interrupt
1 CH1 Mask 0: Generate interrupt if CH1 sync activity, polarity, period, or
pulse width changes.
1: Mask CH1 interrupt
2 N/A Set to 1
3 N/A Set to 1
4 Input Disrupted Mask 0: Generate interrupt if selected Input Channel’s sync inputs
are disrupted.
1: Mask Input Channel interrupt
5 Input Changed Mask 0: Generate interrupt after selected Input Channel period or
pulse width settles to new value.
1: Mask Input Channel interrupt
6 VSYNC INT Mask 0: Generate interrupt every VSYNC
1: Mask VSYNC Interrupt
7 PADJ INT Mask 0: Generate interrupt upon phase adjustment block request
completion.
1: Mask Phase adjustment interrupt
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE) BITS FUNCTION NAME DESCRIPTION
ISL98003
12
FN6760.0
September 12, 2008
CONFIGURATION REGISTERS
0x10 Input Configuration, (0x00) 1:0 Input Channel Select Sets video muxes as well as HSYNC, VSYNC, and SOG input
muxes.
0: CH0
1: CH1
2: N/A
3: N/A
2 N/A Set to 0
3 DC Coupled Input Enable 0: AC-coupled Inputs
1: DC-coupled Inputs
4 RGB YUV 0: RGB inputs (Clamp DAC = 300mV for R, G, B, half scale
analog shift for R, G, and B, base ABLC target code = 0x00
for R, G, and B).
1: YPbPr inputs (Clamp DAC = 600mV for R and B, 300mV for
G, half scale analog shift for G channel only, base ABLC
target code = 0x00 for G, = 0x80 for R and B).
5 N/A Set to 0
6 EXT Clamp SEL 0: Internal CLAMP generation
1: External CLAMP source
7 EXT Clamp POL 0: Active high external CLAMP
1: Active low external CLAMP
0x11 Sync Source Selection,
(0x00)
0 Sync Select 0: Automatic (HSYNC, VSYNC sources selected based on
sync activity. Multiplexer settings chosen are displayed in
the Input Characteristics register).
1: Manual (bits 1and 2 determine HSYNC and VSYNC source)
1 HSYNC Source 0: HSYNC input pin
1: SOG
2 VSYNC Source 0: VSYNC input pin
1: Sync Separator output
0x12 Red Gain MSB, (0x55) 7:0 Red Gain MSB Red channel gain, where: gain (V/V) = 0.5 + [9:0]/682
MSB/LSB
0x00 00: gain = 0.5 V/V (1.4V
P-P
input = full range of ADC)
0x55 00: gain = 1.0 V/V (0.7V
P-P
input = full range of ADC)
0xFF C0: gain = 2.0 V/V (0.35V
P-P
input = full range of ADC)
0x13 Red Gain LSB, (0x00) 5:0 N/A
7:6 Red Gain LSB 2 LSBs of 10-bit gain word
0x14 Green Gain MSB, (0x55) 7:0 Green Gain MSB See Red Gain
0x15 Green Gain LSB, (0x00) 5:0 N/A
7:6 Green Gain LSB See Red Gain
0x16 Blue Gain MSB, (0x55) 7:0 Blue Gain MSB See Red Gain
0x17 Blue Gain LSB, (0x00) 5:0 N/A
7:6 Blue Gain LSB See Red Gain
0x18 Red Offset MSB, (0x80) 7:0 Red Offset MSB ABLC off: upper 8 bits to Red offset DAC
ABLC enabled: Red digital offset
0x00 00 = min DAC value or -0x80 digital offset
0x80 00 = mid DAC value or 0x00 digital offset,
0xFF C0 = max DAC value or +0x7F digital offset
0x19 Red Offset LSB, (0x00) 5:0 N/A
7:6 Red Offset LSB 2 LSBs of 10-bit offset word
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE) BITS FUNCTION NAME DESCRIPTION
ISL98003
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

ISL98003CNZ-165

Mfr. #:
Buy ISL98003CNZ-165
Manufacturer:
Renesas / Intersil
Description:
Analog Front End - AFE ISL98003CNZ 8-BIT VI D ALOG F/E/ AFE165MH
Lifecycle:
New from this manufacturer.
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