8
FN6760.0
September 12, 2008
CLAMP
IN
Digital 3.3V input.When this input is high and external CLAMP is selected, connects the selected channels inputs to the
clamp DAC.
CLOCKINV
IN
Digital 3.3V input. When high, changes the pixel sampling phase by 180°. Toggle at frame rate during VSYNC to allow 2x
undersampling to sample odd and even pixels on sequential frames. Tie to D
GND
if unused.
TEST
OUT
3.3V digital output. A delayed version of internal COAST or CLAMP when selected.
RESET
Digital 3.3V input, active low, 70kΩ pull-up to V
D
. Take low for at least 1µs and then high again to reset the ISL98003. This
pin is not necessary for normal use and may be tied directly to the V
D
supply.
XTAL
IN
Analog input. Connect to external 12MHz to 27MHz crystal and load capacitor (see crystal spec for recommended loading).
Typical oscillation amplitude is 1.0V
P-P
centered around 0.5V.
XTAL
OUT
Analog output. Connect to external 12MHz to 27MHz crystal and load capacitor (see crystal spec for recommended
loading). Typical oscillation amplitude is 1.0V
P-P
centered around 0.5V.
XCLK
OUT
3.3V digital output. Buffered crystal clock output at f
XTAL
or f
XTAL
/2. May be used as system clock for other system
components.
SCL Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
SDA Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
EXTCLK
IN
Digital 3.3V input. External clock input for AFE.
R[7:0] 3.3V digital output. 8-bit Red channel pixel data.
G[7:0] 3.3V digital output. 8-bit Green channel pixel data.
B[7:0] 3.3V digital output. 8-bit Blue channel pixel data.
DATACLK 3.3V digital output. Data (pixel) clock output.
DATACLK
3.3V digital output. Inverse of DATACLK.
HS
OUT
3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data. This output is
always purely horizontal sync (without any composite sync signals).
HSYNC
OUT
3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC period. This
output will pass composite sync signals and Macrovision signals if present on HSYNC
IN
or SOG
IN
.
VSYNC
OUT
3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the duration of the
disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period.
INT
Digital output, open drain, 5V tolerant. Interrupt output indicating mode change or command execution status. Pull high
with a 4.7k resistor.
DE 3.3V digital output. High when there is valid video data, low during horizontal and vertical blanking periods.
FIELD 3.3V digital output. For interlaced video, this output will changes states to indicate whether current field is even or odd.
Polarity is determined by configuration register.
V
A3.3
Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GND with 0.1µF.
V
A1.8
Power supply for the analog section. Connect to a 1.8V supply and bypass each pin to GND with 0.1µF.
VPLL
A3.3
Power supply for the analog PLL section. Connect to a 3.3V supply and bypass to GND with 0.1µF.
GND Ground return connected to exposed pad.
V
D3.3
Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GND with 0.1µF.
V
D1.8
Power supply for digital core logic. Connect to a 1.8V supply and bypass each pin to GND with 0.1µF.
VADC
D1.8
Power supply for the digital ADC section. Connect to a 1.8V supply and bypass to GND with 0.1µF.
VPLL
D1.8
Power supply for the digital PLL section. Connect to a 1.8V supply and bypass to GND with 0.1µF.
DTEST1, 2, 3, 4, 5 For production use only. Tie to GND.
Pin Descriptions (Continued)
SYMBOL DESCRIPTION
ISL98003
