16
FN6760.0
September 12, 2008
0x2D XTAL CLOCK FREQ,
(0x19)
4:0 Crystal Clock Frequency Crystal clock frequency in MHz (decimal).
0x00: Test Mode, Do not use.
0x01 - 0x0A: 10MHz, APLL DIV = 35 (0x23)
0x0B: 11MHz, APLL DIV = 32
0x0C: 12MHz, APLL DIV = 30
0x0D: 13MHz, APLL DIV = 27
0x0E: 14MHz, APLL DIV = 25
0x0F: 15MHz, APLL DIV = 24
0x10: 16MHz, APLL DIV = 22
0x11: 17MHz, APLL DIV = 21
0x12: 18MHz, APLL DIV = 20
0x13: 19MHz, APLL DIV = 19
0x14: 20MHz, APLL DIV = 18
0x15: 21MHz, APLL DIV = 17
0x16: 22MHz, APLL DIV = 16
0x17: 23MHz, APLL DIV = 16
0x18: 24MHz, APLL DIV = 15
0x19: 25MHz, APLL DIV = 14
0x1A: 26MHz, APLL DIV = 14
0x1B: 27MHz, APLL DIV = 13
0x1C: 28MHz, APLL DIV = 13
0x1D: 29MHz, APLL DIV = 13
0x1E: 30MHz, APLL DIV = 12
0x1F: 31MHz, APLL DIV = 12
0x2E AFE Bandwidth, (0x0E) 3:0 AFE BW -3dB point for AFE lowpass filter
0: 9MHz
1: 10MHz
2: 11MHz
3: 12MHz
4: 14MHz
5: 17MHz
6: 21 MHz
7: 24MHz
8: 30MHz
9: 38MHz
A: 50MHz
B: 75MHz
C: 83MHz
D: 105MHz
E: 149MHz (default)
F: 450MHz
0x2F HSYNC Slicer Thresholds,
(0x44)
All values referred to
voltage at HSYNC input pin,
300mV hysteresis
3:0 Selected HSYNC Threshold HSYNC slicer threshold for selected input channel (only 3 bits
used, lowest bit is ignored):
0000 = lowest (0.4V)
0100 = default (1.15V)
1111 = highest (3.2V)
7:4 Unselected HSYNC
Threshold
HSYNC threshold for monitoring unselected inputs. See
Selected HSYNC Threshold for values.
0x30 SOG Slicer Thresholds,
(0x66)
3:0 SOG Threshold SOG slicer threshold:
0000 = lowest (0mV)
0110 = default (120mV)
1111 = highest (300mV)
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE) BITS FUNCTION NAME DESCRIPTION
ISL98003
17
FN6760.0
September 12, 2008
0x31 HSYNC/SOG Config,
(0x04)
3:0 Glitch Filter Width 0: 16 crystal clocks
1: 17 crystal clocks
2: 1 crystal clocks
3: 2 crystal clocks
4: 3 crystal clocks (default)
5: 4 crystal clocks
6: 5 crystal clocks
7: 6 crystal clocks
8: 7 crystal clocks
9: 8 crystal clocks
10: 9 crystal clocks
11: 10 crystal clocks
12: 11crystal clocks
13: 12 crystal clocks
14: 13 crystal clocks
15: 14 crystal clocks
4 Sync Glitch Filter Disable 0: glitch filter enabled
1: glitch filter disabled
5 SOG Hyst Disable 0: 40mV hysteresis enabled
1: 40mV hysteresis disabled
6 SOG LPF Disable 0: 14MHz SOG Low Pass Filter Enabled
1: 14MHz SOG Low Pass Filter Disabled
0x32 Sync Polling Control, (0x00) 0 CH0 Polling 0: Enable
1: Disable
1 CH1 Polling 0: Enable
1: Disable
2 N/A Set to 1
3 N/A Set to 1
4 CH0 Connector Type 0: RGB DB15 (poll for HSYNC, CSYNC, and SOG)
1: Component (poll for SOG only)
5 CH1 Connector Type 0: RGB DB15 (poll for HSYNC, CSYNC, and SOG)
1: Component (poll for SOG only)
6 N/A Set to 0
7 N/A Set to 0
MEASUREMENT REGISTERS
0x40 HSYNC Period MSB,
(read only)
7:0 HSYNC Period MSB These registers report a 16-bit value containing the number of
crystal clocks inside a 16 consecutive HSYNC period window.
This means the 16-bit number will reflect one HSYNC period
with 1/16 LSB resolution - the last 4 -bits of the measurement
will be fractional.
0x41 HSYNC Period LSB,
(read only)
7:0 HSYNC Period LSB
0x42 HSYNC Width MSB,
(read only)
7:0 HSYNC Width MSB These registers report a 16-bit value containing the number of
crystal clocks inside 16 consecutive HSYNC pulses. This
means the 16-bit number will reflect one HSYNC pulse width
with 1/16 LSB resolution - the last 4 bits of the measurement
will be fractional.
0x43 HSYNC Width LSB,
(read only)
7:0 HSYNC Width LSB
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE) BITS FUNCTION NAME DESCRIPTION
ISL98003
18
FN6760.0
September 12, 2008
0x44 VSYNC Period MSB,
(read only)
3:0 VSYNC Period MSB These bit report a 12-bit value containing the width of one
frame (= 2 fields for interlaced, = 1 field for progressive) of
video.
VSYNC period for measured channel = 256* VSYNC Period
MSB + VSYNC Period LSB
Units are either number of HSYNC periods or number of
fCRYSTAL/512 periods, depending on setting of VSYNC Units
register.
0x45 VSYNC Period LSB,
(read only)
7:0 VSYNC Period LSB
0x46 VSYNC Width,
(read only)
6:0 VSYNC Width This register reports a 7-bit value containing the width the
VSYNC pulse. The value returned is for true VSYNC only: it
does not include serrations, EQ pulses, Macrovision pulses,
etc. Units are either number of HSYNC periods or number of
fCRYSTAL/512 periods, depending on setting of VSYNC Units
register.
0x47 DE Start MSB, (0x00) 1:0 DE Start MSB 8-bit value containing the number of pixel clocks between the
trailing edge of HSOUT and the first valid pixel. SXGA default
values.
0x48 DE Start LSB, (0xF6) 7:0 DE Start LSB
0x49 DE Width MSB, (0x05) 3:0 DE Width MSB 12-bit value containing the number of visible image pixels.
SXGA default values.
0x4A DE Width LSB, (0x00) 7:0 DE Width LSB
0x4B Line Start MSB, (0x00) 1:0 Line Start MSB 8-bit value containing the number of lines between the trailing
edge of VSYNC
OUT
and the first valid line. SXGA default
values.
0x4C Line Start LSB, (0x26) 7:0 Line Start LSB
0x4D Line Width MSB, (0x04) 3:0 Line Width MSB 12-bit value containing the number of visible lines.
SXGA default values.
0x4E Line Width LSB, (0x00) 7:0 Line Width LSB
0x4F
Measurement Configuration,
(0x00)
0 VSYNC Units 0: VSYNC measurement reported in units of lines
(HSYNC periods)
1: VSYNC measurement reported in units of 512 crystal clock
periods
1 VSYNC_Linecount_Mode 0: New method (Integer count of HSOUTs)
1: Old method (Time measurement with rounding errors)
AUTO ADJUST REGISTERS
0x50 Phase ADJ CMD FN, (0x00) 2:0 PADJ Function Note: A write to this register executes the command contained
in the three LSBs of the word written. Commands:
000: Reserved
001: Reserved
010: Reserved
011: SetPhase
100: Set DE
101: Reserved
110: Reserved
111: Reserved
0x51 Phase ADJ STATUS,
(read only)
7 PADJ Busy 0: Phase Adjustment function idle
1: Phase Adjustment in progress
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE) BITS FUNCTION NAME DESCRIPTION
ISL98003

ISL98003CNZ-165

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog Front End - AFE ISL98003CNZ 8-BIT VI D ALOG F/E/ AFE165MH
Lifecycle:
New from this manufacturer.
Delivery:
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