4
FN6760.0
September 12, 2008
Offset Adjustment Range
(ABLC Enabled or Disabled)
(see “Automatic Black Level
Compensation (ABLC™) and Gain
Control” on page 21)
±50% ADC
Fullscale
ANALOG VIDEO INPUT CHARACTERISTICS (R
IN
0-1, G
IN
0-1, B
IN
0-1)
Input Range 0.35 0.7 1.4 V
P-P
Input Bias Current DC-restore clamp off ±0.01 ±1 µA
Input Capacitance 5pF
Full Power Bandwidth Programmable 10 to 450 MHz
SOG INPUT CHARACTERISTICS (SOG
IN
0-1)
Sync Tip Clamp 600 mV
SOG Pull-Down A
V
IH
/V
IL
Input Threshold Voltage
(Relative to Bottom of Sync Tip)
Programmable (see “Register Listing”
on page 10)
0 to 0.3 V
Input Capacitance 5pF
HSYNC INPUT CHARACTERISTICS (HSYNC
IN
0-1)
V
IH
/V
IL
Input Threshold Voltage Programmable (see “Register Listing”
on page 10)
0.4 to 3.2 V
Hysteresis Centered around threshold voltage 240 mV
I Input Leakage Current ±10 nA
C
IN
Input Capacitance 5pF
DIGITAL INPUT CHARACTERISTICS (ALL DIGITAL INPUT PINS EXCEPT SCL, VSYNC
IN
0-1)
V
IH
Input High Voltage 2.0 V
V
IL
Input Low Voltage 0.8 V
I Input Leakage Current RESET
has a 65kΩ pull-up to V
D3.3
±10 nA
C
IN
Input Capacitance 5pF
SCHMITT DIGITAL INPUT CHARACTERISTICS (SCL, VSYNC
IN
0-3)
V
T
+ Low to High Threshold Voltage 1.45 V
V
T
- High to Low Threshold Voltage 0.95 V
I Input Leakage Current ±10 nA
C
IN
Input Capacitance 5pF
DIGITAL OUTPUT CHARACTERISTICS (ALL OUTPUT PINS EXCEPT INT
AND SDA)
V
OH
Output HIGH Voltage, I
O
= 8mA 2.4 V
V
OL
Output LOW Voltage, I
O
= -8mA 0.4 V
DIGITAL OUTPUT CHARACTERISTICS (INT
)
V
OL
Output LOW Voltage, I
O
= -8mA Open-drain, with 65kΩ pull-up to V
D3.3
0.4 V
DIGITAL OUTPUT CHARACTERISTICS (SDA)
V
OL
Output LOW Voltage, I
O
= -4mA Open-drain 0.4 V
POWER SUPPLY REQUIREMENTS
V
A3.3
Analog Supply Voltage, 3.3V Includes VPLL
A3.3
3.0 3.3 3.6 V
Electrical Specifications Specifications apply for V
A3.3
= V
D3.3
= V
PLLA3.3
= 3.3V, V
A1.8
= V
D1.8
= V
PLLD1.8
= V
ADCD1.8
= 1.8V,
pixel rate = 110MHz for ISL98003-110, 150MHz for ISL98003-150 and 165MHz for ISL98003-165,
f
XTAL
= 25MHz, and T
A
= +25°C, unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST LEVEL or NOTES
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
ISL98003
5
FN6760.0
September 12, 2008
V
A1.8
Analog Supply Voltage, 1.8V 1.65 1.8 2.0 V
V
D3.3
Digital Supply Voltage, 3.3V 3.0 3.3 3.6 V
V
D1.8
Digital Supply Voltage, 1.8V Includes VADC
D1.8
, VPLL
D1.8
1.65 1.8 2.0 V
I
A3.3
Analog Supply Current, 3.3V
(Note 4)
40 90 mA
IPLL
A3.3
14 25 mA
I
A1.8
Analog Supply Current, 1.8V
(Note 4)
Includes 1.8V ADC reference current
draw
280 375 mA
I
D3.3
Digital Supply Current, 3.3V
(Note 4)
Grayscale ramp input 40 60 mA
I
D1.8
Digital Supply Current, 1.8V
(Note 4)
Grayscale ramp input 65 95 mA
IADC
D1.8
33 65 mA
IPLL
D1.8
1.8 10 mA
P
D
Total Power Dissipation Grayscale ramp input
Standby Mode
0.95 1.1 W
50 100 mW
AC TIMING CHARACTERISTICS
PLL Jitter (Note 5) 250 450 ps p-p
Sampling Phase Steps 5.6° per step 64
Sampling Phase Tempco ±1 ps/°C
Sampling Phase
Differential Nonlinearity
Degrees out-of-phase +360° ±3 °
HSYNC Frequency Range 10 150 kHz
f
XTAL
Crystal Frequency Range 12 25 27 MHz
t
SETUP
Data Valid Before Rising Edge of
DATACLK
20pF DATACLK load,
20pF DATA load
1.8 ns
t
HOLD
Data Valid After Rising Edge of
DATACLK
20pF DATACLK load,
20pF DATA load
3.4 ns
NOTES:
3. Linearity tested at room temperature and established across commercial temperature range by correlation to characterization.
4. Supply current specified at max pixel rate (165MHz) with gray scale video applied.
5. Jitter tested at rated frequencies (110MHz, 150MHz and 165MHz) and at minimum frequency (10MHz).
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Electrical Specifications Specifications apply for V
A3.3
= V
D3.3
= V
PLLA3.3
= 3.3V, V
A1.8
= V
D1.8
= V
PLLD1.8
= V
ADCD1.8
= 1.8V,
pixel rate = 110MHz for ISL98003-110, 150MHz for ISL98003-150 and 165MHz for ISL98003-165,
f
XTAL
= 25MHz, and T
A
= +25°C, unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST LEVEL or NOTES
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
ISL98003
6
FN6760.0
September 12, 2008
Timing Diagrams
Data Output Setup and Hold Timing
RGB Output Data Timing and Latency
YUV Output Data Timing and Latency
PIXEL DATA
DATACLK
t
HOLD
t
SETUP
DATACLK
PROGRAMMABLE
WIDTH AND POLARITY
ANALOG
VIDEO IN
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
D
0
R/G/B[7:0]
HS
OUT
8 DATACLK PIPELINE LATENCY
P
10
P
11
P
12
D
1
D
2
D
3
HSYNC
IN
THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED
TO. THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST
OF THE AFE’S OUTPUT SIGNALS
DATACLK
PROGRAMMABLE
WIDTH AND POLARITY
ANALOG
VIDEO IN
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
HS
OUT
8 DATACLK PIPELINE LATENCY
P
10
P
11
P
12
HSYNC
IN
THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED TO.
THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST OF THE
AFE’S OUTPUT SIGNALS
DATACLK
G
0
(Y
O
) G
1
(Y
1
)G
2
(Y
2
)
B
0
(U
O
)R
0
(V
0
)B
2
(U
2
)
G[7:0]
R[7:0]
B[7:0]
G
3
(Y
3
)
R
2
(V
2
)
ISL98003

ISL98003CNZ-165

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog Front End - AFE ISL98003CNZ 8-BIT VI D ALOG F/E/ AFE165MH
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union