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ISL98003CNZ-165

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
25
FN6760.0
September 12, 2008
The default Offset DAC range is ±127 ADC LSBs. Setting
0x27[1] = 1 reduces the swing of the Offset DAC by 50%,
making 1 Offset DAC LSB the weight of 1/8 of an ADC LSB.
This provides the finest offset control and applies to both
ABLC™ and manual modes.
Automatic Black Level Compensation (ABLC)
ABLC is a function that continuously removes all offset
errors from the incoming video signal by monitoring the
offset at the output of the ADC and servoing the 10-bit
analog DAC to force those errors to zero. When ABLC is
enabled, the user offset control is a digital adder, with 8-bit
resolution.
When the ABLC function is enabled (0x27[0] = 0), the ABLC
function is executed every line after the trailing edge of
HSYNC. If register 0x60[2] = 0 (the default), the ABLC
function will be not be triggered while the DPLL is coasting,
preventing any composite sync edges, equalization pulses,
or Macrovision signals from corrupting the black data and
potentially adding a small error in the ABLC accumulator.
After the trailing edge of HSYNC, the start of ABLC is
delayed by the number of pixels specified in registers 0x24
and 0x25. After that delay, the number of pixels specified
by register 0x27[3:2] are averaged together and added to
the ABLC’s accumulator. The accumulator stores the
average black levels for the number of lines specified by
register 0x27[6:4], which is then used to generate a 10-bit
DAC value.
The ABLC can be set to allow the capture of signals below
black by setting registers 0x65, 0x66 and 0x67 to a number
that will control the target for the ABLC servo loop. If you set
register 0x65 to 0x10 then the ABLC will adjust the offset
DAC to produce an average output code on the Red channel
of 0x10 during the back porch. Effectively, the black level for
a given channel will be set to the value of its ABLC offset
target register (output = register 0x65, 0x66 or 0x67).
ADC
The ISL98003 features 3 fully differential, high-speed 8-bit
ADCs.
Clock Generation
A Digital Phase Lock Loop (DPLL) is employed to generate
the pixel clock frequency. The HSYNC input and the external
XTAL provide a reference frequency to the PLL. The PLL
then generates the pixel clock frequency that equal to the
incoming HSYNC frequency times the HTOTAL value
programmed into registers 0x1E and 0x1F.
The stability of the clock is very important and correlates
directly with the quality of the image. During each pixel time
transition, there is a small window where the signal is
slewing from the old pixel amplitude and settling to the new
pixel value. At higher frequencies, the pixel time transitions
at a faster rate, which makes the stable pixel time even
smaller. Any jitter in the pixel clock reduces the effective
stable pixel time and thus the sample window in which pixel
sampling can be made accurately.
Sampling Phase
The ISL98003 provides 64 low-jitter phase choices per pixel
period, allowing the firmware to precisely select the optimum
sampling point. The sampling phase register is 0x20.
Auto Phase Adjust
The ISL98003 provides the ability to automatically adjust the
Sampling Phase to the best setting. Set register 0x50 to
0x03 to activate the auto phase adjust function.
Data Enable (DE) Generator
The ISL98003 provides a signal that is high during the active
video time when properly configured. This signal is used by
devices such as DVI/HDMI transmitters to gate the active
portion of the video and ignore the H and V sync times.
Auto DE Adjust
The ISL98003 provides the ability to automatically adjust the
DE to the settings that are very close to ideal. The
determination of exactly where on a line the active video
starts and ends depends heavily on the video content being
analyzed making the DE settings difficult to automate. The
customer will be required to fine tune the DE settings after
the Auto Adjust routine has completed. Set register 0x50 to
0x04 to activate the auto DE adjust function
HSYNC Slicer
To further minimize jitter, the HSYNC inputs are treated as
analog signals, and brought into a precision slicer block with
thresholds programmable in 400mV steps with 240mV of
hysteresis, and a subsequent digital glitch filter that ignores
any HSYNC transitions within 100ns of the initial transition.
This processing greatly increases the AFE’s rejection of
ringing and reflections on the HSYNC line and allows the
AFE to perform well even with pathological HSYNC signals.
Voltages given above and in the HSYNC Slicer register
description are with respect to a 3.3V sync signal at the
HSYNC
IN
input pin. To achieve 5V compatibility, a 1kΩ series
resistor should be placed between the HSYNC source and the
HSYNC
IN
input pin and a 1.9kΩ resistor should be placed
between the HSYNC
IN
input pin and ground. Relative to a 5V
input, the hysteresis will be 240mV*5V/3.3V = 360mV, and the
slicer step size will be 400mV*5V/3.3V = 600mV per step.
SYNC Status and Polarity Detection
The CH0 and CH1 Activity Status register (0x02)
continuously monitors all 6 sync inputs (VSYNC
IN
,
HSYNC
IN
, and SOG
IN
for both of the channels) and report
their status while the Selected Input Channel Characteristics
register (0x01) gives more detailed information on the
currently selected input channel.
However, accurate sync activity detection is always a
challenge. Noise and repetitive video patterns on the Green
ISL98003
26
FN6760.0
September 12, 2008
channel may look like SOG activity when there actually is no
SOG signal, while non-standard SOG signals and TriLevel
sync signals may have amplitudes below the default SOG
slicer levels and not be easily detected. As a consequence,
not all of the activity detect bits in the ISL98003 are correct
under all conditions.
For best SOG operation, the SOG low pass filter (register
0x31[6] should always be enabled to reject the high
frequency peaking often seen on video signals.
HSYNC and VSYNC Activity Detect
Activity on these bits always indicates valid sync pulses, so
they should have the highest priority and be used even if the
SOG activity bit is also set.
SOG Activity Detect
The SOG activity detect bit monitors the output of the SOG
slicer, looking for 64 consecutive pulses with the same
period and duty cycle. If there is no signal on the Green
(or Y) channel, the SOG slicer will clamp the video to a DC
level and will reject any sporadic noise. There should be no
false positive SOG detects if there is no video on Green
(or Y).
If there is video on Green (or Y) with no valid SOG signal,
the SOG activity detect bit may sometimes report false
positives (it will detect SOG when no SOG is actually
present). This is due to the presence of video with a
repetitive pattern that creates a waveform similar to SOG.
For example, the desktop of a PC operating system is black
during the front porch, horizontal sync, and back porch, then
increases to a larger value for the video portion of the
screen. This creates a repetitive video waveform very similar
to SOG that may falsely trigger the SOG Activity detect bit.
However, in these cases where there is active video without
SOG, the SYNC information will be provided either as
separate H and V sync on HSYNC
IN
and VSYNC
IN
, or
composite sync on HSYNC
IN
. HSYNC
IN
and VSYNC
IN
should therefore be used to qualify SOG. The SOG Active bit
should only be considered valid if HSYNC Activity
Detect = 0. Note: Some pattern generators can output
HSYNC and SOG simultaneously, in which case both the
HSYNC and the SOG activity bits will be set, and valid. Even
in this case, however, the monitor should still choose
HSYNC over SOG.
TriLevel Sync Detect
The TriLevel detect for Sync on Green (SOG) utilizes the
digitized data from the selected Green video channel. If
TriLevel Sync is present, the default DC Clamp start position
will clamp at the top of the TriLevel Sync pulse giving a false
negative for TriLevel detect and clamping off the bottom half
of the green video. If you have an indication of active SOG
you must move the clamp start to a value greater than 0x30
to check to see if the TriLevel Sync is present.
SYNC Output Signals
The ISL98003 has a pair of HSYNC output signals,
HSYNC
OUT
and VSYNC
OUT
, and HS
OUT
.
HSYNC
OUT
and VSYNC
OUT
are buffered versions of the
incoming sync signals; no synchronization is done. These
signals are used for mode detection
HS
OUT
is generated by the ISL98003’s logic and is
synchronized to the output DATACLK and the digital pixel
data on the output databus. HS
OUT
is used to signal the
start of a new line of digital data.
Both HSYNC
OUT
and VSYNC
OUT
(including the sync
separator function) remain active in power-down mode. This
allows them to be used in conjunction with the Sync Status
registers to detect valid video without powering up the
ISL98003.
HSYNC
OUT
HSYNC
OUT
is an unmodified, buffered version of the incoming
HSYNC
IN
or SOG
IN
signal of the selected channel, with the
incoming signal’s period, polarity, and width to aid in mode
detection. HSYNC
OUT
will be the same format as the incoming
sync signal: either horizontal or composite sync. If a SOG input
is selected, HSYNC
OUT
will output the entire SOG signal,
including the VSYNC portion, pre-/post-equalization pulses if
present, and Macrovision pulses if present. HSYNC
OUT
remains active when the ISL98003 is in power-down mode.
HSYNC
OUT
is generally used for mode detection.
VSYNC
OUT
VSYNC
OUT
is an unmodified, buffered version of the incoming
VSYNC
IN
signal of the selected channel, with the original
VSYNC period, polarity, and width to aid in mode detection. If a
SOG input is selected, this signal will output the VSYNC signal
extracted by the ISL98003’s sync slicer. Extracted VSYNC will
be the width of the embedded VSYNC pulse plus pre- and
post-equalization pulses (if present). Macrovision pulses from
an NTSC DVD source will lengthen the width of the VSYNC
pulse. Macrovision pulses from other sources (PAL DVD or
videotape) may appear as a second VSYNC pulse
encompassing the width of the Macrovision. See “Macrovision”
on page 23 for more information. VSYNC
OUT
(including the
sync separator function) remains active in power-down mode.
VSYNC
OUT
is generally used for mode detection, start of field
detection, and even/odd field detection.
HS
OUT
HS
OUT
is generated by the ISL98003’s control logic and is
synchronized to the output DATACLK and the digital pixel data
on the output databus. Its trailing edge is aligned with pixel 0. Its
width, in units of pixels, is determined by register 0x2A, and its
polarity is determined by register 0x29[3]. As the width is
increased, the trailing edge stays aligned with pixel 0, while the
leading edge is moved backwards in time relative to pixel 0.
HS
OUT
is used by the scaler to signal the start of a new line of
pixels.
ISL98003
27
FN6760.0
September 12, 2008
Crystal Oscillator
An external 12MHz to 27MHz crystal supplies the low-jitter
reference clock to the DPLL. The absolute frequency of this
crystal within this range is unimportant, as is the crystal’s
temperature coefficient, allowing use of less expensive,
lower-grade crystals.
As an alternative to a crystal, the XTAL
IN
pin can be driven
with a 3.3V CMOS-level external clock source at any
frequency between 12MHz and 27MHz. The ISL98003’s
jitter specification assumes a low-jitter crystal source. If the
external clock source has increased jitter, the sample clock
generated by the DPLL may exhibit increased jitter as well.
EMI Considerations
There are two possible sources of EMI on the ISL98003, as
follows.
CRYSTAL OSCILLATOR
The EMI from the crystal oscillator is negligible. This is due to
an amplitude-regulated, low voltage sine wave oscillator circuit,
instead of the typical high-gain square wave inverter-type
oscillator, so there are no harmonics. The crystal oscillator is
not a significant source of EMI.
DIGITAL OUTPUT SWITCHING
This is the largest potential source of EMI. However, the EMI is
determined by the PCB layout and the loading on the databus.
The way to control this is to put series resistors on the output of
all the digital pins (as our demo board and reference circuits
show). These resistors should be as large as possible, while
still meeting the setup and hold timing requirements of the
scaler. We recommend starting with 22Ω. If the databus is
heavily loaded (long traces, many other part on the same bus),
this value may need to be reduced. If the databus is lightly
loaded, it may be increased.
Intersil’s recommendations to minimize EMI are:
• Minimize the databus trace length
• Minimize the databus capacitive loading.
If EMI is a problem in the final design, increase the value of the
digital output series resistors to reduce slew rates on the bus.
This can only be done as long as the scaler’s setup and hold
timing requirements continue to be met.
Standby Mode
The ISL98003 can be placed into a low power standby mode
by writing a 0x0F to register 0x2C, powering down the triple
ADCs, the DPLL, and most of the internal clocks.
To allow input monitoring and mode detection during
power-down, the following blocks remain active:
• Serial interface (including the crystal oscillator) to enable
register read/write activity
• Activity and polarity detect functions (registers 0x01 and
0x02)
• The HSYNC
OUT
and VSYNC
OUT
pins (for mode detection)
Initialization
The ISL98003 initializes with default register settings for an
AC-coupled, RGB input on the VGA1 channel.
Reset
The ISL98003 has a Power On Reset (POR) function that
resets the chip to its default state when power is initially
applied, including resetting all the registers to their default
settings as described in the “Register Listing” on page 10.
The POR function takes 512k Crystal clocks (~21ms at
25MHz) to complete. The external RESET
pin duplicates the
reset function of the POR without having to cycle the power
supplies. The RESET
pin does not need to be used in
normal operation and can be tied high.
ISL98003 Serial Communication
Overview
The ISL98003 uses a 2-wire serial bus for communication
with its host. SCL is the Serial Clock line, driven by the host,
and SDA is the Serial Data line, which can be driven by all
devices on the bus. SDA is open drain to allow multiple
devices to share the same bus simultaneously.
Communication is accomplished in three steps:
1. The Host selects the ISL98003 it wishes to communicate
with.
2. The Host writes the initial ISL98003 Configuration
Register address it wishes to write to or read from.
3. The Host writes to or reads from the ISL98003’s
Configuration Register. The ISL98003’s internal address
pointer auto increments, so to read registers 0x00
through 0x1B, for example, one would write 0x00 in
Step 2, then repeat Step 3 (28) times, with each read
returning the next register value.
The ISL98003 has a 7-bit address (1001100) on the serial
bus.
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START
command by taking SDA low while SCL is high (Figure 3).
The ISL98003 continuously monitors the SDA and SCL lines
for the start condition and will not respond to any command
until this condition has been met. The host then transmits the
7-bit serial address plus a R/W
bit, indicating if the next
transaction will be a Read (R/W
= 1) or a Write (R/W = 0). If
the address transmitted matches that of any device on the
bus, that device must respond with an ACKNOWLEDGE
(see Figure 4).
ISL98003
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

ISL98003CNZ-165

Mfr. #:
Buy ISL98003CNZ-165
Manufacturer:
Renesas / Intersil
Description:
Analog Front End - AFE ISL98003CNZ 8-BIT VI D ALOG F/E/ AFE165MH
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