ISL98003CNZ-165 Datasheet ISL98003CNZ-165, ISL98003CNZ-EVALZ, ISL98003INZ-EVALZ | P13-P15

FN6760.0

September 12, 2008

0x1A Green Offset MSB, (0x80) 7:0 Green Offset MSB ABLC off: upper 8 bits to Green offset DAC

ABLC enabled: Green digital offset

(See Red Offset)

0x1B Green Offset LSB, (0x00) 5:0 N/A

7:6 Green Offset LSB See Red Offset

0x1C Blue Offset MSB, (0x80) 7:0 Blue Offset MSB ABLC off: upper 8 bits to Blue offset DAC

ABLC enabled: Blue digital offset

(See Red Offset)

0x1D Blue Offset LSB, (0x00) 5:0 N/A

7:6 Blue Offset LSB See Red Offset

0x1E PLL HTOTAL MSB, (0x06) 5:0 PLL HTOTAL MSB 14-bit HTOTAL

PLL updated on LSB write only.

0x1F PLL HTOTAL LSB, (0x98) 7:0 PLL HTOTAL LSB PLL updated on LSB write only. SXGA default

0x20 PLL Phase, (0x00) 5:0 PLL Sampling Phase Used to control the phase of the ADC’s sample point relative

to the period of a pixel. Adjust to obtain optimum image quality.

One step = 5.625° (1.56% of pixel period).

0x21 PLL Pre-coast, (0x04) 7:0 Pre-coast Number of lines the PLL will coast prior to the start of VSYNC.

0x22 PLL Post-coast, (0x04) 7:0 Post-coast Number of lines the PLL will coast after the end of VSYNC.

0x23 PLL Misc, (0x00) 0 PLL Lock Edge HSYNC 0: PLL locks to trailing edge of selected HSYNC (default)

1: PLL locks to leading edge of selected HSYNC

1 CLKINV ENABLE 0: CLKINV input ignored

1: CLKINV input enabled

2 Ext Coast SEL 0: Internal COAST generation

1: External COAST source

3 Ext Coast POL 0: Active high external COAST

1: Active low external COAST

4 EXT CLOCK 0: Internal pixel clock from DPLL

1: External pixel clock from EXTCLKin pin

0x24 DC-Restore and ABLC

starting pixel MSB, (0x00)

5:0 DC-Restore and ABLC

starting pixel (MSB)

Pixel after Raw HSYNC trailing edge to begin DC-restore and

ABLC. 14 bits.

0x25 DC-Restore and ABLC

starting pixel LSB, (0x02)

7:0 DC-Restore and ABLC

starting pixel (LSB)

0x26 DC-Restore Clamp Width,

(0x10)

7:0 DC-Restore clamp width Only applies to DC-restore clamp used for AC-coupled

configurations. A value of 0x00 means the clamp DAC is never

connected to the input.

ADDRESS

(DEFAULT VALUE) BITS FUNCTION NAME DESCRIPTION

ISL98003

FN6760.0

September 12, 2008

0x27 ABLC Configuration, (0x40) 0 ABLC Disable 0: ABLC on (default) - use 8-bit digital offset control.

0x000 = -0x200 LSB offset, 0x3FF = +0x1FF LSB offset,

0x200 = 0x000 LSB offset.

1: ABLC off - use 8-bit offset DACs, bypass digital adder

(add/subtract nothing, but keep same delay through

channel).

1 Offset DAC Range 0: ±1/2 ADC fullscale (1 LSB = 0.25 ADC LSBs)

1: ±1/4 ADC fullscale (1 LSB = 0.165 ADC LSBs)

3:2 ABLC Pixel Width Number of black pixels averaged every line for ABLC function

00: 16 pixels [default]

01: 32 pixels

10: 64 pixels

11: 128 pixels

6:4 ABLC Bandwidth ABLC Time constant (lines) = 2

([5+6:4])

000 = 32 lines

100 = 512 lines (default)

111 = 4096 lines

0x28 Output Format 1, (0x00) 0 Data Output Format 0: 4:4:4 (24-bit output)

1: 4:2:2 (16-bit output on G and R)

1 4:2:2 Order 0: First pixel on R channel is U

1: First pixel on R channel is V

2 4:2:2 Processing 0: U, V filtered (high quality)

1: Odd U, V pixels dropped (lower quality)

3 8-bit Mode Should be set to 1

5:4 Oversampling 00: Normal operation (1x sampling)

01:2x oversampling, 2 samples averaged at ADC output

10:4x oversampling, 4 samples averaged at ADC output

11:8x oversampling, 8 samples averaged at ADC output

In Oversampling mode, the HTOTAL, DC-Restore/ABLC Start,

DC-Restore Width, and ABLC width values are automatically

multiplied by the oversampling ratio. The pixel clock is divided

by the oversampling ratio when the data is decimated.

Decimator is reset on trailing edge of HSYNC.

6 RGB2YUV Color Space

Conversion Enable

0: CSC Disabled

1: CSC Enabled

Note: The data delay through the entire AFE is identical with

CSC on and CSC off.

ADDRESS

(DEFAULT VALUE) BITS FUNCTION NAME DESCRIPTION

ISL98003

FN6760.0

September 12, 2008

0x29 Output Format 2, (0x00) 0 DATACLK Polarity 0: Pixel data changes on falling edge (default)

1: Pixel data changes on rising edge

1 FIELD output polarity 0: Odd = low, Even = high (default)

1: Odd = high, Even = low

2 Macrovision 0: Digitize Macrovision encoded signals (default)

1: Blank AFE output for Macrovision encoded signals. If

Macrovision is detected, AFE output is always 0x00, 0x00,

0x00 for RGB, or 0x00, 0x80, 0x80 for YUV.

3 HSOUT Polarity 0: Active High (default)

1: Active Low

4 HSOUT Lock Edge 0: HSOUT’s leading edge is locked to selected HSYNC

’s

lock edge. Trailing edge moves forward in time as HSOUT

width is increased (default).

1: HSOUT’s trailing edge is locked to selected HSYNC

’s

lock edge. Leading edge moves backward in time as

HSOUT width is increased.

5 XTALCLKOUT Frequency 0: XTALCLKOUT = f

CRYSTAL

(default)

1: XTALCLKOUT = f

CRYSTAL

6 Enable XTALCLKOUT 0 = XTALCLKOUT is logic low (default)

1 = XTALCLKOUT enabled

0x2A HSOUT Width, (0x10) 7:0 HSOUT Width HSOUT Width in pixels, 0x00 to 0xFF. HSOUT Lock Edge

determines whether leading or trailing edge is locked to

HSYNCin.

0x2B Output Signal Disable,

(0xFF)

Note: All digital outputs are

tri-stated by default to ease

multiplexing with other

AFEs

0 Tri-state Red 0 = Outputs enabled

1 = Outputs in tri-state

1 Tri-state Green 0 = Outputs enabled

1 = Outputs in tri-state

2 Tri-state Blue 0 = Outputs enabled

1 = Outputs in tri-state

3 Tri-state SYNC 0 = HSOUT, HSYNC

OUT

, VSYNC

OUT

enabled

1 = Outputs in tri-state

4 Tri-state DATACLK 0 = Output enabled

1 = Output in tri-state

5 Tri-state DATACLKb 0 = Output enabled

1 = Output in tri-state

6 Tri-state DE 0 = Output enabled

1 = Output in tri-state

7 Tri-state Field 0 = Output enabled

1 = Output in tri-state

0x2C Power Control, (0x00) 0 Red Power-Down 0 = Red ADC operational (default)

1 = Red ADC powered down

1 Green Power-Down 0 = Green ADC operational (default)

1 = Green ADC powered down

2 Blue Power-Down 0 = Blue ADC operational (default)

1 = Blue ADC powered down

3 PLL Power-Down 0 = PLL operational (default)

1 = PLL powered down

ADDRESS

(DEFAULT VALUE) BITS FUNCTION NAME DESCRIPTION

ISL98003

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P31

ISL98003CNZ-165

Mfr. #:

Buy ISL98003CNZ-165

Manufacturer:

Renesas / Intersil

Description:

Analog Front End - AFE ISL98003CNZ 8-BIT VI D ALOG F/E/ AFE165MH

Lifecycle:

New from this manufacturer.

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ISL98003CNZ-165

ISL98003CNZ-165

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