LTC2655IUF-H12#TRPBF Datasheet LTC2655IGN-H12#PBF, LTC2655BIGN-H16#PBF, LTC2655IGN-L12#PBF | P19-P21

LTC2655

2655f

The LTC2655 is a family of quad voltage output DACs in

20-lead 4mm × 4mm QFN and in 16-lead narrow SSOP

packages. Each DAC can operate rail-to-rail in external

reference mode, or with its full-scale voltage set by an

integrated reference. Four combinations of accuracy (16-bit

and 12-bit), and full-scale voltage (2.5V or 4.096V) are

available. The LTC2655 is controlled using a 2-wire I

compatible interface.

Power-On Reset

The LTC2655-L/LTC2655-H clear the output to zero-scale

if PORSEL pin is tied to GND, when power is ﬁ rst applied,

making system initialization consistent and repeatable. For

some applications, downstream circuits are active during

DAC power-up, and may be sensitive to nonzero outputs

from the DAC during this time. The LTC2655 contains

circuitry to reduce the power-on glitch. The analog outputs

typically rise less than 10mV above zero-scale during power

on if the power supply is ramped to 5V in 1ms or more.

In general, the glitch amplitude decreases as the power

supply ramp time is increased. See Power-On Reset Glitch

in the Typical Performance Characteristics section.

Alternatively, if PORSEL pin is tied to V

, The LTC2655-L/

LTC2655-H set the output to mid-scale when power is

ﬁ rst applied.

Power Supply Sequencing and Start-Up

For the LTC2655 family of parts, the internal reference is

powered up at start-up by default. If an external reference

is to be used, REFCOMP (Pin 3/Pin 2, GN/UF) must be

hardwired to GND. This conﬁ guration allows the use of an

external reference at start-up and converts the REFIN/OUT

pin to an input. However, the internal reference will still be

ON and draw supply current. In order to use an external

reference, command 0111b should be used to turn the

internal reference off (see Table 1).

The voltage at REFIN/OUT (Pin 5/Pin 4, GN/UF) should be

kept within the range – 0.3V ≤ REFIN/OUT ≤ V

+ 0.3V

(see the Absolute Maximum Ratings section). Particular

care should be taken to observe these limits during power

supply turn-on and turn-off sequences, when the voltage

at V

(Pin 15/Pin 18, GN/UF) is in transition.

Transfer Function

The digital-to-analog transfer function is

OUT(IDEAL)

= 2 • k/2

REF

– REFLO] + REFLO

where k is the decimal equivalent of the binary DAC input

code, N is the resolution, and V

REF

is the voltage at the

REFIN/OUT Pin. The resulting DAC output span is 0V to

2•V

REF

, as it is necessary to tie REFLO to GND. V

REF

nominally 1.25V for LTC2655-L and 2.048V for LTC2655-H,

in internal reference mode.

Table 1

COMMAND*

C3 C2 C1 C0

0 0 0 0 Write to Input Register

0 0 0 1 Update (Power-Up) DAC Register

0 0 1 0 Write to Input Register

, Update (Power-Up) All

0 0 1 1 Write to and Update (Power-Up)

0 1 0 0 Power-Down

0 1 0 1 Power-Down Chip (All DAC’s and Reference)

0 1 1 0 Select Internal Reference (Power-Up Reference)

0 1 1 1 Select External Reference (Power-Down Reference)

1 1 1 1 No Operation

ADDRESS (

A3 A2 A1 A0

0 0 0 0 DAC A

0 0 0 1 DAC B

0 0 1 0 DAC C

0 0 1 1 DAC D

1 1 1 1 All DACs

* Command and address codes not shown are reserved and should not

be used.

Serial Interface

The LTC2655 communicates with a host using the stan-

dard 2-wire I

C interface. The Timing Diagram (Figure 1)

shows the timing relationship of the signals on the bus.

The two bus lines, SDA and SCL, must be high when the

bus is not in use. External pull-up resistors or current

sources are required on these lines. The value of these

pull-up resistors is dependent on the power supply and

can be obtained from the I

C speciﬁ cations. For an I

bus operating in the fast mode, an active pull-up will be

OPERATION

LTC2655

2655f

necessary if the bus capacitance is greater than 200pF.

The LTC2655 is a receive-only (slave) device. The master

can write to the LTC2655. The LTC2655 does not respond

to a read command from the master.

The START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be high.

A bus master signals the beginning of a communication

to a slave device by transmitting a START condition (see

Figure 1). A START condition is generated by transitioning

SDA from high to low while SCL is high. When the master

has ﬁ nished communicating with the slave, it issues a STOP

condition. A STOP condition is generated by transitioning

SDA from low to high while SCL is high. The bus is then

free for communication with another I

C device.

Acknowledge

The Acknowledge signal is used for handshaking between

the master and the slave. An Acknowledge (active LOW)

generated by the slave lets the master know that the lat-

est byte of information was received. The Acknowledge

related clock pulse is generated by the master. The master

releases the SDA line (HIGH) during the Acknowledge

clock pulse. The slave-receiver must pull down the SDA

bus line during the Acknowledge clock pulse so that it

remains a stable LOW during the HIGH period of this clock

pulse. The LTC2655 responds to a write by a master in

this manner. The LTC2655 does not acknowledge a read

(retains SDA HIGH during the period of the Acknowledge

clock pulse).

Chip Address

The state of CA0, CA1 and CA2 decides the slave address

of the part. The pins CA0, CA1 and CA2 can be each set

to any one of three states: V

, GND or ﬂ oat. This results

in 27 selectable addresses for the part. The slave address

assignments are shown in Table 2.

In addition to the address selected by the address pins,

the parts also respond to a global address. This address

allows a common write to all LTC2655 parts to be accom-

plished with one 3-byte write transaction on the I

C bus.

The global address is a 7-bit on-chip hardwired address

and is not selectable by CA0, CA1 and CA2. The addresses

corresponding to the states of CA0, CA1 and CA2 and

the global address are shown in Table 2. The maximum

capacitive load allowed on the address pins (CA0, CA1

and CA2) is 10pF, as these pins are driven during address

detection to determine if they are ﬂ oating.

Table 2. Slave Address Map

CA2 CA1 CA0 A6 A5 A4 A3 A2 A1 A0

GND GND GND 0 0 1 0 0 0 0

GND GND FLOAT 0 0 1 0 0 0 1

GND GND V

0010010

GND FLOAT GND 0 0 1 0 0 1 1

GND FLOAT FLOAT 0 1 0 0 0 0 0

GND FLOAT V

0100001

GND V

GND 0 1 0 0 0 1 0

GND V

FLOAT 0 1 0 0 0 1 1

GND V

0110000

FLOAT GND GND 0 1 1 0 0 0 1

FLOAT GND FLOAT 0 1 1 0 0 1 0

FLOAT GND V

0110011

FLOAT FLOAT GND 1 0 0 0 0 0 0

FLOAT FLOAT FLOAT 1 0 0 0 0 0 1

FLOAT FLOAT V

1000010

FLOAT V

GND 1 0 0 0 0 1 1

FLOAT V

FLOAT 1 0 1 0 0 0 0

FLOAT V

1010001

GND GND 1 0 1 0 0 1 0

GND FLOAT 1 0 1 0 0 1 1

GND V

1100000

FLOAT GND 1 1 0 0 0 0 1

FLOAT FLOAT 1 1 0 0 0 1 0

FLOAT V

1100011

GND 1 1 1 0 0 0 0

FLOAT 1 1 1 0 0 0 1

1110010

GLOBAL ADDRESS 1 1 1 0 0 1 1

OPERATION

LTC2655

2655f

OPERATION

Write Word Protocol

The master initiates communication with the LTC2655

with a START condition and a 7-bit slave address followed

by the Write bit (W) = 0. The LTC2655 acknowledges by

pulling the SDA pin low at the 9th clock if the 7-bit slave

address matches the address of the part (set by CA0, CA1

and CA2) or the global address. The master then transmits

three bytes of write data. The LTC2655 acknowledges each

byte of data by pulling the SDA line low at the 9th clock of

each data byte transmission. After receiving three com-

plete bytes of data, the LTC2655 executes the command

speciﬁ ed in the 24-bit input word. If more than three data

bytes are transmitted after a valid 7-bit slave address, the

LTC2655 does not acknowledge the extra bytes of data

(SDA is high during the 9th clock). The ﬁ rst byte of the

input word consists of the 4-bit command followed by

the 4-bit address. The next two bytes consist of the 16-bit

data word. The 16-bit data word consists of the 16-bit, or

12-bit input code, MSB to LSB, followed by 0 or 4 don’t

care bits (LTC2655-16 and LTC2655-12 respectively). A

typical LTC2655 write transaction is shown in Figure 2.

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 1. The ﬁ rst four commands in the table

consist of write and update operations. A write operation

loads a 16-bit data word from the 32-bit shift register into

the input register. In an update operation, the data word

is copied from the input register to the DAC register and

converted to an analog voltage at the DAC output. The

update operation also powers up the DAC if it had been in

power-down mode. The data path and registers are shown

in the Block Diagram.

Power-Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever less

than four outputs are needed. When in power-down, the

buffer ampliﬁ ers, bias circuits and integrated reference

circuits are disabled, and draw essentially zero current.

The DAC outputs are put into a high-impedance state, and

the output pins are passively pulled to ground through

individual 80k resistors. Input- and DAC-register contents

are not disturbed during power-down.

Any channel or combination of channels can be put into

power-down mode by using command 0100b in combina-

tion with the appropriate DAC address, (

). The integrated

reference is automatically powered down when external

reference mode is selected using command 0111b. In ad-

dition, all the DAC channels and the integrated reference

together can be put into power-down mode using the

Power-Down Chip command 0101b. For all power-down

commands the 16-bit data word is ignored, but still required

in order to complete a full communication cycle.

Normal operation resumes by executing any command

which includes a DAC update, in software as shown in

Table 1 or using the asynchronous LDAC pin. The selected

DAC is powered up as its voltage output is updated. When

a DAC which is in a powered-down state is powered up and

updated, normal settling is delayed. If less than four DACs

are in a powered-down state prior to the update command,

the power-up delay time is approximately 12s. If on the

other hand, all four DACs and the integrated reference

are powered down, then the main bias generation circuit

block has been automatically shut down in addition to the

individual DAC ampliﬁ ers and the integrated reference.

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LTC2655IUF-H12#TRPBF

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Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC 12-Bit I2C Quad DAC (2.048V Reference)

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LTC2655IUF-H12#TRPBF

LTC2655IUF-H12#TRPBF

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