LTC2655
22
2655f
In this case, the power-up delay time is approximately
14s. The power-up of the integrated reference depends
on the command that powered it down. If the reference is
powered down using the Select External Reference com-
mand (0111b), then it can only be powered back up by
sending the Select Internal Reference command (0110b).
However if the reference was powered down by sending
the Power-Down Chip command (0101b), then in addition
to the Select Internal Reference command (0110b), any
command that powers up the DACs will also power-up
the integrated reference.
Reference Modes
For applications where an accurate external reference is
not available, the LTC2655 has a user-selectable, inte-
grated reference. The LTC2655-L has a 1.25V reference
that provides a full-scale output of 2.5V. The LTC2655-H
has a 2.048V reference that provides a full-scale output
of 4.096V. Both references exhibit a typical temperature
drift of 2ppm/°C. Internal reference mode can be selected
by using command 0110b, and is the power-on default. A
buffer is needed if the internal reference is required to drive
external circuitry. For reference stability and low noise, it
is recommended that a 0.1µF capacitor be tied between
REFCOMP and GND. In this confi guration, the internal
reference can drive up to 0.1µF capacitive load without any
stability problems. In order to ensure stable operation, the
capacitive load on the REFIN/OUT pin should not exceed
the capacitive load on the REFCOMP pin.
The DAC can also operate in external reference mode using
command 0111b. In this mode, the REFIN/OUT pin acts
as an input that sets the DAC’s reference voltage. This
input is high impedance and does not load the external
reference source. The acceptable voltage range at this
pin is 0.5V ≤ REFIN/OUT ≤ V
CC
/2. The resulting full-scale
output voltage is 2V
REFIN/OUT
. For using external refer-
ence at start-up, see the Power Supply Sequencing and
Start-Up Sections.
Integrated Reference Buffers
Each of the four DACs in LTC2655 has its own integrated
high performance reference buffer. The buffers have very
high input impedance and do not load the reference volt-
age source. These buffers shield the reference voltage
from glitches caused by DAC switching and thus minimize
DAC-to-DAC dynamic crosstalk. By tying 0.22F capacitors
between REFCOMP and GND, and also between REFIN/OUT
and GND, the crosstalk can be reduced to less than 1nVs.
See the curve DAC-to-DAC Crosstalk (Dynamic) in the
Typical Performance Characteristics section.
Voltage Outputs
Each of the four rail-to-rail amplifi ers contained in LTC2655
has guaranteed load regulation when sourcing or sinking
up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplifi ers ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed
in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The amplifi ers’ DC output
impedance is 0.040 when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30 typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30 • 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The amplifi ers are stable driving capacitive loads of up
to 1000pF.
OPERATION
LTC2655
23
2655f
Board Layout
The excellent load regulation and DC crosstalk performance
of these devices is achieved in part by keeping signal and
power grounds separate.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground. The REFLO pin should be connected to system
star ground. Resistance from the REFLO pin to system
star ground should be as low as possible.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown in
Figure 3b. Similarly, limiting can occur in external refer-
ence mode near full scale when the REFIN/OUT pin is at
V
CC
/2. If V
REFIN/OUT
= V
CC
/2 and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits
at V
CC
as shown in Figure 3c. No full-scale limiting can
occur if V
REFIN/OUT
≤ (V
CC
– F
SE
)/2.
Offset and linearity are defi ned and tested over the region
of the DAC transfer function where no output limiting can
occur.
OPERATION
LTC2655
24
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OPERATION
Figure 2. Typical LTC2655 Input Waveform—Programming DAC Output for Full-Scale
ACK ACK
123456789123456789123456789123456789
2655 F02
ACK
START STOP
FULL-SCALE
VOLTAGE
ZERO-SCALE
VOLTAGE
SDA
SA6 SA5 SA4 SA3 SA2 SA1 SA0
SCL
V
OUT
C2C3
C3 C2 C1 C0 A3 A2 A1 A0
C1 C0 A3 A2 A1 A0
ACK
COMMAND
D15 D14 D13 D12 D11 D10 D9 D8
MS DATA
D7 D6 D5 D4 D3 D2 D1 D0
LS DATA
SA6 SA5 SA4 SA3 SA2 SA1 SA0 WR
SLAVE ADDRESS

LTC2655IUF-H12#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12-Bit I2C Quad DAC (2.048V Reference)
Lifecycle:
New from this manufacturer.
Delivery:
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