© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 5
1 Publication Order Number:
NCP1608/D
NCP1608
Critical Conduction Mode
PFC Controller Utilizing a
Transconductance Error
Amplifier
The NCP1608 is an active power factor correction (PFC)
controller specifically designed for use as a pre−converter in ac−dc
adapters, electronic ballasts, and other medium power off−line
converters (typically up to 350 W). It uses critical conduction mode
(CrM) to ensure near unity power factor across a wide range of input
voltages and output power. The NCP1608 minimizes the number of
external components by integrating safety features, making it an
excellent choice for designing robust PFC stages. It is available in
a SOIC−8 package.
General Features
Near Unity Power Factor
No Input Voltage Sensing Requirement
Latching PWM for Cycle−by−Cycle On Time Control (Voltage
Mode)
Wide Control Range for High Power Application (>150 W) Noise
Immunity
Transconductance Error Amplifier
High Precision Voltage Reference (±1.6% Over the Temperature
Range)
Very Low Startup Current Consumption ( 35 mA)
Low Typical Operating Current Consumption (2.1 mA)
Source 500 mA/Sink 800 mA Totem Pole Gate Driver
Undervoltage Lockout with Hysteresis
Pin−to−Pin Compatible with Industry Standards
This is a Pb−Free and Halide−Free Device
Safety Features
Overvoltage Protection
Undervoltage Protection
Open/Floating Feedback Loop Protection
Overcurrent Protection
Accurate and Programmable On Time Limitation
Typical Applications
Solid State Lighting
Electronic Light Ballast
AC Adapters, TVs, Monitors
All Off−Line Appliances Requiring Power Factor Correction
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAM
PIN CONNECTION
1
8
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
1608B
ALYW
G
1
8
FB
Control
Ct
CS
V
CC
DRV
GND
ZCD
(Top View)
Device Package Shipping
ORDERING INFORMATION
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
NCP1608BDR2G SOIC−8
(Pb−Free)
2500 / Tape & Ree
l
www.onsemi.com
NCP1608
www.onsemi.com
2
Figure 1. Typical Application
+
AC Line
EMI
Filter
1
4
3
2
8
5
6
7
+
C
bulk
LOAD
(Ballast,
SMPS, etc.)
NCP1608
V
out
R
sense
C
in
R
ZCD
R
out1
R
out2
C
COMP
V
CC
C
t
D
L
FB
Control
Ct
CS
GND
ZCD
DRV
V
CC
V
in
N
B
:N
ZCD
M
Figure 2. Block Diagram
E/A
Demag
UVP
Fault
OCP
LEB
Off Timer
Reset
PWM
R
QS
(Enable EA)
Haversine
DRV
R
sense
Q
All SR Latches are Reset Dominant
ZCD Clamp
OVP
UVLO
UVLO
V
CC
DRV
GND
POK
mV
DD
V
CC
mV
DD
POK
V
DD
V
CC
V
DDGD
V
DD
Reg
+
+
-
V
out
C
bulk
R
out1
R
out2
D
FB
Control
ZCD
R
ZCD
C
t
C
t
CS
C
COMP
L
+
+
+
V
OVP
POK
+
V
UVP
R
FB
V
REF
+
g
m
+
V
Control
mV
DD
V
DDGD
R
QS
Q
R
QS
Q
R
QS
Q
R
QS
Q
V
ZCD(TRIG)
+
+
V
ZCD(ARM)
+
V
ILIM
+
+
+
V
DD
Add Ct
Offset
I
charge
V
EAH
Clamp
+
N
B
:N
ZCD
V
in
M
NCP1608
www.onsemi.com
3
Table 1. PIN FUNCTION DESCRIPTION
Pin Name Function
1 FB The FB pin is the inverting input of the internal error amplifier. A resistor divider scales the output voltage to V
REF
to
maintain regulation. The feedback voltage is used for overvoltage and undervoltage protections. The controller is disabled
when this pin is forced to a voltage less than V
UVP
, a voltage greater than V
OVP
, or floating.
2 Control The Control pin is the output of the internal error amplifier. A compensation network is connected between the Control pin
and ground to set the loop bandwidth. A low bandwidth yields a high power factor and a low Total Harmonic Distortion (THD).
3 Ct The Ct pin sources a current to charge an external timing capacitor. The circuit controls the power switch on time by
comparing the Ct voltage to an internal voltage derived from V
Control
. The Ct pin discharges the external timing capacitor
at the end of the on time.
4 CS The CS pin limits the cycle−by−cycle current through the power switch. When the CS voltage exceeds V
ILIM
, the drive
turns off. The sense resistor that connects to the CS pin programs the maximum switch current.
5 ZCD The voltage of an auxiliary winding is sensed by this pin to detect the inductor demagnetization for CrM operation.
6 GND The GND pin is analog ground.
7 DRV The integrated driver has a typical source impedance of 12 W and a typical sink impedance of 6 W.
8 V
CC
The V
CC
pin is the positive supply of the controller. The controller is enabled when V
CC
exceeds V
CC(on)
and is disabled
when V
CC
decreases to less than V
CC(off)
.
Table 2. MAXIMUM RATINGS
Rating Symbol Value Unit
FB Voltage V
FB
−0.3 to 10 V
FB Current I
FB
±10 mA
Control Voltage V
Control
−0.3 to 6.5 V
Control Current I
Control
−2 to 10 mA
Ct Voltage V
Ct
−0.3 to 6 V
Ct Current I
Ct
±10 mA
CS Voltage V
CS
−0.3 to 6 V
CS Current I
CS
±10 mA
ZCD Voltage V
ZCD
−0.3 to 10 V
ZCD Current I
ZCD
±10 mA
DRV Voltage V
DRV
−0.3 to V
CC
V
DRV Sink Current I
DRV(sink)
800 mA
DRV Source Current I
DRV(source)
500 mA
Supply Voltage V
CC
−0.3 to 20 V
Supply Current I
CC
±20 mA
Power Dissipation (TA = 70°C, 2.0 Oz Cu, 55 mm
2
Printed Circuit Copper Clad) P
D
450 mW
Thermal Resistance Junction−to−Ambient
(2.0 Oz Cu, 55 mm
2
Printed Circuit Copper Clad)
Junction−to−Air, Low conductivity PCB (Note 3)
Junction−to−Air, High conductivity PCB (Note 4)
R
q
JA
R
q
JA
R
q
JA
178
168
127
°C/W
Operating Junction Temperature Range (Note 5) T
J
−55 to +125 °C
Maximum Junction Temperature T
J(MAX)
150 °C
Storage Temperature Range T
STG
−65 to +150 °C
Lead Temperature (Soldering, 10 s) T
L
300 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1 – 8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E.
Pins 1– 8: Charged Device Model 1000 V per JEDEC Standard JESD22−C101E.
2. This device contains Latch−Up protection and exceeds ±100 mA per JEDEC Standard JESD78.
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm
2
of 2 oz copper traces and heat spreading area. As specified for
a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm
2
of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
5. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.

NCP1608BDR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Power Factor Correction - PFC COST EFFECT PWR FACT CONT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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