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NCP1608BDR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
NCP1608
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13
A resistor divider (R
out1
and R
out2
) scales down the boost
output voltage (V
out
) and is connected to the FB pin. If the
output voltage is less than the target output voltage, then
V
FB
is less than V
REF
and the EA increases the control
voltage (V
Control
). This increases the on time of the driver,
which increases the power delivered to the output. The
increase in delivered power causes V
out
to increase until the
target output voltage is achieved. Alternatively, if V
out
is
greater than the target output voltage, then V
Control
decreases to cause the on time to decrease until V
out
decreases to the target output voltage. This cause and effect
regulates V
out
so that the scaled down V
out
that is applied
to FB through R
out1
and R
out2
is equal to V
REF
. The
presence of R
FB
(4.6 MW typical value) for FPP is included
in the divider network calculation.
The output voltage is set using Equation 2:
V
out
+ V
REF
@
ǒ
R
out1
@
R
out2
) R
FB
R
out2
@ R
FB
) 1
Ǔ
(eq. 2)
The divider network bias current is selected to optimize
the tradeoff of noise immunity and power dissipation. R
out1
is calculated using the bias current and output voltage using
Equation 3:
R
out1
+
V
out
I
bias(out)
(eq. 3)
Where I
bias(out)
is the output divider network bias current.
R
out2
is dependent on V
out
, R
out1
, and R
FB
.
R
out2
is calculated using Equation 4:
R
out2
+
R
out1
@ R
FB
R
FB
@
ǒ
V
out
V
REF
* 1
Ǔ
* R
out1
(eq. 4)
The PFC stage consumes a sinusoidal current from a
sinusoidal line voltage. The converter provides the load
with a power that matches the average demand only. The
output capacitor (C
bulk
) compensates for the difference
between the delivered power and the power consumed by
the load. When the power delivered to the load is less than
the power consumed by the load, C
bulk
discharges. When
the delivered power is greater than the power consumed by
the load, C
bulk
charges to store the excess energy. The
situation is depicted in Figure 30.
Figure 30. Output Voltage Ripple for a Constant Output Power
V
out
P
out
P
in
Iac
Vac
Due to the charging/discharging of C
bulk
, V
out
contains
a ripple at a frequency of either 100 Hz (for a 50 Hz line
frequency in Europe) or 120 Hz (for a 60 Hz line frequency
in the USA). The V
out
ripple is attenuated by the regulation
loop to ensure V
Control
is constant during the ac line cycle
for the proper shaping of the line current. To ensure V
Control
is constant during the ac line cycle, the loop bandwidth is
typically set below 20 Hz. A type 1 compensation network
consists of a capacitor (C
COMP
) connected between the
Control and ground pins (see Figure 1). The capacitor value
that sets the loop bandwidth is calculated using Equation 5:
C
COMP
+
gm
2 @ p @ f
CROSS
(eq. 5)
Where f
CROSS
is the crossover frequency and gm is the
error amplifier transconductance. The crossover frequency
is set below 20 Hz.
On Time Sequence
The switching pattern consists of constant on times and
variable off times for a given rms input voltage and output
load. The NCP1608 controls the on time with the capacitor
connected to the Ct pin. A current source charges the Ct
capacitor to a voltage derived from the Control pin voltage
(V
Ct(off)
). V
Ct(off)
is calculated using Equation 6:
V
Ct(off)
+ V
Control
−Ct
(offset)
+
2
@
P
out
@
L
@
I
charge
h @ Vac
2
@ Ct
(eq. 6
)
When V
Ct(off)
is reached, the drive turns off (Figure 31).
NCP1608
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14
Figure 31. On Time Generation
Control
Ct
+
−
PWM
+
DRV
I
charge
t
on
V
Control
− Ct
(offset)
t
on
V
Ct
V
Ct(off)
V
DD
DRV
V
Control
Ct
(offset)
V
Control
varies with the rms input voltage and output
load, which naturally satisfies Equation 1. The on time is
constant during the ac line cycle if the values of
compensation components are sufficient to filter out the
V
out
ripple. The maximum on time of the controller occurs
when V
Control
is at the maximum. The Ct capacitor is sized
to ensure that the required on time is reached at maximum
output power and the minimum input voltage condition.
The on time is calculated using Equation 7:
t
on
+
Ct @ V
Ct(MAX)
I
charge
(eq. 7)
Combining Equation 7 with Equation 1, results in
Equation 8:
Ct w
2 @ P
out
@ L
MAX
@ I
charge
h @ Vac
LL
2
@ V
Ct(MAX)
(eq. 8)
To calculate the minimum Ct value:
V
Ct(MAX)
= 4.775 V (minimum value),
I
charge
= 297 mA (maximum value), Vac
LL
is the
minimum rms input voltage, and L
MAX
is the maximum
inductor value.
Off Time Sequence
In CrM operation, the on time is constant during the ac
line cycle and the off time varies with the instantaneous
input voltage. When the inductor current reaches zero, the
drain voltage (V
drain
in Figure 27) resonates towards V
in
.
Measuring V
drain
is a way to determine when the inductor
current reaches zero. To measure the high voltage V
drain
directly is generally not economical or practical. Instead,
a winding is added to the boost inductor. This winding,
called the Zero Current Detection (ZCD) winding,
provides a scaled representation of the inductor voltage
that is sensed by the controller. Figure 32 shows waveforms
of ideal CrM operation using a ZCD winding.
Figure 32. Ideal CrM Waveforms Using a ZCD
Winding
DRV
0 A
0 V
0 V
0 V
0 V
Diode Conduction
MOSFET Conduction
T
SW
t
on
t
diode
t
off
V
CL(NEG)
V
ZCD(TRIG)
V
ZCD(ARM)
V
CL(POS)
V
ZCD(WIND),on
V
ZCD
V
ZCD(WIND),off
V
ZCD(WIND)
V
out
V
drain
I
L(peak)
I
L
The voltage induced on the ZCD winding during the switch
on time (V
ZCD(WIND),on
) is calculated using Equation 9:
V
ZCD(WIND),on
+
−V
in
N
B
:N
ZCD
(eq. 9)
Where V
in
is the instantaneous input voltage and N
B
:N
ZCD
is the turns ratio of the boost winding to the ZCD winding.
The voltage induced on the ZCD winding during the
switch off time (V
ZCD(WIND),off
) is calculated using
Equation 10:
V
ZCD(WIND),off
+
V
out
* V
in
N
B
:N
ZCD
(eq. 10)
When the inductor current reaches zero, the ZCD pin
voltage (V
ZCD
) follows the ZCD winding voltage
(V
ZCD(WIND)
) and begins to decrease and ring towards zero
volts. The NCP1608 detects the falling edge of V
ZCD
and
turns the driver on. To ensure that a ZCD event is not
inadvertently detected, the NCP1608 logic verifies that
V
ZCD
exceeds V
ZCD(ARM)
and then senses that V
ZCD
decreases to less than V
ZCD(TRIG)
(Figure 33).
NCP1608
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15
Figure 33. Implementation of the ZCD Block
ZCD
+
−
+
Demag
+
−
+
Reset
Dominant
Latch
R
QS
DRIVE
ZCD Clamp
R
ZCD
V
in
N
ZCD
N
B
R
sense
V
ZCD(ARM)
V
ZCD(TRIG)
Q
This sequence achieves CrM operation. The maximum
V
ZCD(ARM)
sets the maximum turns ratio and is calculated
using Equation 11:
N
B
:N
ZCD
v
V
out
*
ǒ
2
Ǹ
@ Vac
HL
Ǔ
V
ZCD(ARM)
(eq. 11)
Where Vac
HL
is the maximum rms input voltage and
V
ZCD(ARM)
= 1.55 V (maximum value).
The NCP1608 prevents excessive voltages on the ZCD
pin by clamping V
ZCD
. When the ZCD winding is negative,
the ZCD pin is internally clamped to V
CL(NEG)
. Similarly,
when the ZCD winding is positive, the ZCD pin is
internally clamped to V
CL(POS)
. A resistor (R
ZCD
in
Figure 33) is necessary to limit the current into the ZCD
pin. The maximum ZCD pin current (I
ZCD(MAX)
) is limited
to less than 10 mA. R
ZCD
is calculated using Equation 12:
R
ZCD
w
2
Ǹ
@ Vac
HL
I
ZCD(MAX)
@ (N
B
:N
ZCD
)
(eq. 12)
The value of R
ZCD
and the parasitic capacitance of the
ZCD pin determine when the ZCD winding signal is
detected and the drive turn on begins. A large R
ZCD
value
creates a long delay before detecting the ZCD event. In this
case, the controller operates in DCM and the power factor
is reduced. If the R
ZCD
value is too small, the drive turns
on when the drain voltage is high and efficiency is reduced.
A popular strategy for selecting R
ZCD
is to use the R
ZCD
value that achieves minimum drain voltage turn on. This
value is found experimentally. Figure 34 shows the realistic
waveforms for CrM operation due to R
ZCD
and the ZCD pin
capacitance.
Figure 34. Realistic CrM Waveforms Using a ZCD
Winding with R
ZCD
and the ZCD Pin Capacitance
DRV
0 A
0 V
0 V
0 V
0 V
Diode Conduction
MOSFET Conduction
t
z
R
ZCD
Delay
Minimum Voltage Turn on
t
on
t
off
T
SW
t
diode
V
CL(NEG)
V
ZCD(TRIG)
V
ZCD(ARM)
V
CL(POS)
V
ZCD(WIND),on
V
ZCD
V
ZCD(WIND),off
V
ZCD(WIND)
V
out
V
drain
I
L(peak)
I
L
I
L(NEG)
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NCP1608BDR2G

Mfr. #:
Buy NCP1608BDR2G
Manufacturer:
ON Semiconductor
Description:
Power Factor Correction - PFC COST EFFECT PWR FACT CONT
Lifecycle:
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