NCP1608
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16
During the delay caused by R
ZCD
and the ZCD pin capacitance, the equivalent drain capacitance (C
EQ(drain)
) discharges
through the path shown in Figure 35.
Figure 35. Equivalent Drain Capacitance Discharge Path
+
AC Line
EMI
Filter
+
D
L
I
in
C
in
I
L
C
bulk
V
out
C
EQ(drain)
C
EQ(drain)
is the combined parasitic capacitances of the
MOSFET, the diode, and the inductor. C
in
is charged by the
energy discharged by C
EQ(drain)
. The charging of C
in
reverse biases the bridge rectifier and causes the input
current (I
in
) to decrease to zero. The zero input current
causes THD to increase. To reduce THD, the ratio (t
z
/ T
SW
)
is minimized, where t
Z
is the period from when I
L
= 0 A to
when the drive turns on. The ratio (t
z
/ T
SW
) is inversely
proportional to the square root of L.
During startup, there is no energy in the ZCD winding
and no voltage signal to activate the ZCD comparators.
This means that the drive never turns on. To enable the PFC
stage to start under these conditions, an internal watchdog
timer (t
start
) is integrated into the controller. This timer
turns the drive on if the drive has been off for more than
165 ms (typical value). This feature is deactivated during a
fault mode (OVP or UVP), and reactivated when the fault
is removed.
Wide Control Range
The Ct charging threshold (V
Ct(off)
) decreases as the
output power is decreased from the maximum output
power to the minimum output power in the application. In
high power applications (> 150 W), V
Control
is reduced to
a low voltage at a large output power and Ct
(offset)
remains
constant. The result is that V
Ct(off)
is reduced to a low
voltage at a large output power. The low V
Control
and
V
Ct(off)
voltages are susceptible to noise. The large output
power combined with the low V
Control
and V
Ct(off)
increase
the probability of noise interfering with the control signals
and on time duration (Figures 36 and 37). The noise induces
voltage spikes on the Control pin and Ct pin that reduces the
drive on time from the on time determined by the feedback
loop (t
on(loop)
). The reduced on time causes the energy
stored in the inductor (L) to be reduced. The result is that
V
ZCD
does not exceed V
ZCD(ARM)
and the drive remains off
until t
start
expires. This sequence results in pulse skipping
and reduced power factor.
Figure 36. Control Pin Noise Induced On Time
Reduction and Pulse Skipping
DRV Remains Off
DRV
is Not Exceeded
0 V
Noise Induced Voltage Spike
t
start
t
on
t
on(loop)
V
ZCD(ARM)
Low V
Control
Voltage
Low V
Ct(off)
Voltage
V
Control
− Ct
(offset)
V
Control
Ct
(offset)
V
Ct
V
Ct(off)
V
ZCD
V
ZCD(ARM)
V
ZCD(TRIG)
V
CL(NEG)
NCP1608
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17
Figure 37. Ct Pin Noise Induced On Time
Reduction and Pulse Skipping
Noise Induced Voltage Spike
DRV Remains Off
DRV
is Not Exceeded
0 V
t
on
t
start
t
on(loop)
V
CL(NEG)
V
ZCD(TRIG)
V
ZCD
V
ZCD(ARM)
V
ZCD(ARM)
V
Ct(off)
V
Ct
V
Control
Ct
(offset)
Low V
Control
Voltage
Low V
Ct(off)
Voltage
V
Control
− Ct
(offset)
The wide control range of the NCP1608 increases
V
Control
and V
Ct(off)
in comparison to devices with less
control range. Figure 38 compares V
Ct(off)
of the NCP1608
to a device with a 3 V control range for an application with
the following parameters:
P
out
= 250 W
L = 200 mH
h = 92%
Va c
LL
= 85 Vac
Va c
HL
= 265 Vac
Figure 38 shows that V
Ct(off)
of the NCP1608 is 50%
larger than the 3 V control range device. The 50% increase
enables the NCP1608 to prevent inadvertent skipping at
high input voltages and high output power.
P
out
, OUTPUT POWER (W)
V
Ct(off)
, Ct CHARGING THRESHOLD (V)
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
25 75 125 175 225 275
Figure 38. Comparison of Ct Charging Threshold
vs. Output Power
NCP1608
V
in
= 265 Vac
3 V Control
Range
Startup
Generally, a resistor connected between the rectified ac
line and V
CC
charges the V
CC
capacitor to V
CC(on)
. The low
startup current consumption (< 35 mA) enables minimized
standby power dissipation and reduced startup durations.
When V
CC
exceeds V
CC(on)
, the internal references and
logic of the NCP1608 are enabled. The controller includes
an undervoltage lockout (UVLO) feature that ensures that
the NCP1608 is enabled until V
CC
decreases to less than
V
CC(off)
. This hysteresis ensures sufficient time for the
auxiliary winding to supply V
CC
(Figure 39).
Figure 39. Typical V
CC
Startup Waveform
V
CC
V
CC(on)
V
CC(off)
When the PFC pre-converter is loaded by a switch−mode
power supply (SMPS), it is generally preferable for the
SMPS controller to startup first. The SMPS then supplies
the NCP1608 V
CC
. Advanced controllers, such as the
NCP1230 or NCP1381, control the enabling of the PFC
stage (see Figure 40) and achieve optimal system
performance. This sequence eliminates the startup resistors
and improves the standby power dissipation of the system.
NCP1608
www.onsemi.com
18
Figure 40. NCP1608 Supplied by a Downstream SMPS Controller (NCP1230)
1
7
6
5
2
3
4
NCP1608
+
+
+
+
1
7
6
5
2
3
4
NCP1230
PFC(Vcc)
88
+
D
C
bulk
V
CC
+
Soft Start
When V
CC
exceeds V
CC(on)
, t
start
begins counting. When
t
start
expires, the error amplifier is enabled and begins
charging the compensation network. The drive is enabled
when V
Control
exceeds Ct
(offset)
. The charging of the
compensation network slowly increases the drive on time
from the minimum time (t
PWM
) to the steady state on time.
This creates a natural soft start mode that reduces the stress
of the power components (Figure 41).
Output Driver
The NCP1608 includes a powerful output driver capable
of sourcing 500 mA and sinking 800 mA. This enables the
controller to drive power MOSFETs efficiently for medium
power ( 350 W) applications. Additionally, the driver
stage provides both passive and active pull−down circuits
(Figure 42). The pull−down circuits force the driver output
to a voltage less than the turn−on threshold voltage of a
power MOSFET when V
CC(on)
is not reached.
Figure 41. Startup Timing Diagram Showing the
Natural Soft Start of the Control Pin
FB
Control
Natural Soft Start
V
CC(on)
V
CC(off)
V
CC
I
switch
V
REF
Ct
(offset)
V
out
t
start
Figure 42. Output Driver Stage and Pull−Down Circuits
UVLO
DRV
GND
+
+
DRV IN
UVLO
V
CC
V
DD
REG
V
DD
V
ddGD
mV
DD

NCP1608BDR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Power Factor Correction - PFC COST EFFECT PWR FACT CONT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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