NCP1608
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22
BOOST DESIGN EQUATIONS Components are identified in Figure 1
Input rms Current
Iac +
P
out
h @ Vac
h (the efficiency of only the PFC
stage) is generally in the range of
90 − 95%. Vac is the rms ac line
input voltage.
Inductor Peak Current
I
L(peak)
+
2
Ǹ
@ 2 @ P
out
h @ Vac
The maximum inductor peak current
occurs at the minimum line input
voltage and maximum output power.
Inductor Value
L v
Vac
2
@
ǒ
V
out
2
Ǹ
* Vac
Ǔ
@ h
2
Ǹ
@ V
out
@ P
out
@ f
SW(MIN)
f
SW(MIN)
is the minimum desired
switching frequency. The maximum L
is calculated at both the minimum
line input voltage and maximum line
input voltage.
On Time
t
on
+
2 @ L @ P
out
h @ Vac
2
The maximum on time occurs at the
minimum line input voltage and
maximum output power.
Off Time
t
off
+
t
on
V
out
Vac@
Ť
sinq
Ť
@ 2
Ǹ
* 1
The off time is a maximum at the
peak of the ac line voltage and
approaches zero at the ac line zero
crossings. Theta (q) represents the
angle of the ac line voltage.
Switching Frequency
f
SW
+
Vac
2
@ h
2 @ L @ P
out
@ ǒ1 *
Vac @
|
sinq
|
@ 2
Ǹ
V
out
Ǔ
On Time Capacitor
Ct w
2 @ P
out
@ L
MAX
@ I
charge
h @ Vac
LL
2
@ V
Ct(MAX)
Where Vac
LL
is the minimum line
input voltage and L
MAX
is the
maximum inductor value. I
charge
and
V
Ct(MAX)
are shown in the
specification table.
Inductor Turns to ZCD
Turns Ratio
N
B
:N
ZCD
v
V
out
*
ǒ
2
Ǹ
@ Vac
HL
Ǔ
V
ZCD(ARM)
Where Vac
HL
is the maximum line
input voltage. V
ZCD(ARM)
is shown in
the specification table.
Resistor from ZCD
Winding to the ZCD pin
R
ZCD
w
2
Ǹ
@ Vac
HL
I
ZCD(MAX)
@ (N
B
:N
ZCD
)
Where I
ZCD(MAX)
is maximum rated
current for the ZCD pin (10 mA).
Output Voltage and Output
Divider
V
out
+ V
REF
@
ǒ
R
out1
@
R
out2
) R
FB
R
out2
@ R
FB
) 1
Ǔ
R
out1
+
V
out
I
bias(out)
R
out2
+
R
out1
@ R
FB
R
FB
@
ǒ
V
out
V
REF
* 1
Ǔ
* R
out1
Where V
REF
is the internal reference
voltage and R
FB
is the pull−down
resistor used for FPP. V
REF
and R
FB
are shown in the specification table.
I
bias(out)
is the bias current of the
output voltage divider.
Output Voltage OVP
Detection and Recovery
V
out(OVP)
+
V
OVP
V
REF
@ V
REF
@
ǒ
R
out1
@
R
out2
) R
FB
R
out2
@ R
FB
) 1
Ǔ
V
out(OVPL)
+ ǒ
ǒ
V
OVP
V
REF
@ V
REF
Ǔ
−V
OVP(HYS)
Ǔ@
ǒ
R
out1
@
R
out2
) R
FB
R
out2
@ R
FB
) 1
Ǔ
V
OVP
/V
REF
and V
OVP(HYS)
are
shown in the specification table.
Output Voltage Ripple and
Output Capacitor Value
C
bulk
w
P
out
2 @ p @ V
ripple(peak−peak)
@ f
line
@ V
out
V
ripple(peak−peak)
t 2 @
ǒ
V
out(OVP)
* V
out
Ǔ
Where f
line
is the ac line frequency
and V
ripple(peak−peak)
is the
peak-to-peak output voltage ripple.
Use f
line
= 47 Hz for universal input
worst case.
Output Capacitor rms
Current
I
C(RMS)
+
2
Ǹ
@ 32 @ P
out
2
9 @ p @ Vac @ V
out
@ h
2
* I
load(RMS)
2
Ǹ
Where I
load(RMS)
is the rms load
current.
NCP1608
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23
BOOST DESIGN EQUATIONS Components are identified in Figure 1 (Continued)
Output Voltage UVP
Detection
V
out(UVP)
+ V
UVP
@
ǒ
R
out1
@
R
out2
) R
FB
R
out2
@ R
FB
) 1
Ǔ
V
UVP
is shown in the specification
table.
Inductor rms Current
I
L(RMS)
+
2 @ P
out
3
Ǹ
@ Vac @ h
Output Diode rms
Current
I
D(RMS)
+
4
3
@
2
Ǹ
@ 2
p
Ǹ
@
P
out
h @ Vac @ V
out
Ǹ
MOSFET rms Current
I
M(RMS)
+
2
3
Ǹ
@
ǒ
P
out
h @ Vac
Ǔ
@ 1 *
ǒ
2
Ǹ
@ 8 @ Vac
3 @ p @ V
out
Ǔ
Ǹ
Current Sense Resistor
R
sense
+
V
ILIM
I
L(peak)
P
R
sense
+ I
M(RMS)
2
@ R
sense
V
ILIM
is shown in the specification
table.
Type 1 Compensation
C
COMP
+
gm
2 @ p @ f
CROSS
Where f
CROSS
is the crossover
frequency and is typically less than
20 Hz. gm is shown in the
specification table.
NCP1608
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24
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) Z
S
X
S
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒ
mm
inches
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
P
UBLICATION ORDERING INFORMATION
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Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
NCP1608/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Order Literature: http://www.onsemi.com/orderlit
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cal
Sales Representative
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SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent− Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty,
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are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or
for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products
for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against
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NCP1608BDR2G

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Manufacturer:
ON Semiconductor
Description:
Power Factor Correction - PFC COST EFFECT PWR FACT CONT
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