PCF8576C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 13 — 16 December 2013 18 of 62
NXP Semiconductors
PCF8576C
Universal LCD driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCF8576C are timed by the frequency
f
clk
, which equals either the built-in oscillator frequency f
osc
or the external clock frequency
f
clk(ext)
.
The clock frequency (f
clk
) determines the LCD frame frequency (f
fr
) and the maximum rate
for data reception from the I
2
C-bus. To allow I
2
C-bus transmissions at their maximum data
rate of 100 kHz, f
clk
should be chosen to be above 125 kHz.
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to pin V
SS
. In this case, the
output from pin CLK is the clock signal for any cascaded PCF8576C in the system.
7.5.2 External clock
Connecting pin OSC to V
DD
enables an external clock source. Pin CLK then becomes the
external clock input.
Remark: A clock signal must always be supplied to the device. Removing the clock,
freezes the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing
The timing of the PCF8576C sequences the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal (SYNC
) maintains the correct timing
relationship between the PCF8576Cs in the system. The timing also generates the LCD
frame frequency which is derived as an integer division of the clock frequency (see
Table 7
). The frame frequency is set by the mode-set command (see Table 10) when an
internal clock is used or by the frequency applied to the pin CLK when an external clock is
used.
[1] The possible values for f
clk
see Table 17.
[2] For f
clk
= 200 kHz.
[3] For f
clk
= 31 kHz.
The ratio between the clock frequency and the LCD frame frequency depends on the
power mode in which the device is operating. In the power-saving mode, the reduction
ratio is six times smaller; this allows the clock frequency to be reduced by a factor of six.
The reduced clock frequency results in a significant reduction in power consumption.
Table 7. LCD frame frequencies
[1]
Power mode Frame frequency Nominal frame frequency (Hz)
Normal-power mode 69
[2]
Power-saving mode
65
[3]
f
fr
f
clk
2880
-------------
=
f
fr
f
clk
480
----------
=
