PCF8576C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 13 — 16 December 2013 19 of 62
NXP Semiconductors
PCF8576C
Universal LCD driver for low multiplex rates
The lower clock frequency has the disadvantage of increasing the response time when
large amounts of display data are transmitted on the I
2
C-bus. When a device is unable to
process a display data byte before the next one arrives, it holds the SCL line LOW until
the first display data byte is stored. This slows down the transmission rate of the I
2
C-bus
but no data loss occurs.
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
7.8 Shift register
The shift register transfers display information from the display RAM to the display register
while previous data is displayed.
7.9 Segment outputs
The LCD drive section includes 40 segment outputs, S0 to S39, which must be connected
directly to the LCD. The segment output signals are generated based on the multiplexed
backplane signals and with data residing in the display register. When less than
40 segment outputs are required, the unused segment outputs should be left open-circuit.
7.10 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated based on the selected LCD drive mode.
• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required, the unused outputs can be left as an
open-circuit.
• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities.
• In static drive mode: the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.11 Display RAM
The display RAM is a static 40 4-bit RAM which stores LCD data.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
