PCF8576C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 13 — 16 December 2013 9 of 62
NXP Semiconductors
PCF8576C
Universal LCD driver for low multiplex rates
The host microprocessor or microcontroller maintains the 2-line I
2
C-bus communication
channel with the PCF8576C.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to V
SS
. The only other connections required to complete the system are the
power supplies (pins V
DD
, V
SS
, and V
LCD
) and the LCD panel selected for the application.
7.1 Power-On-Reset (POR)
At power-on the PCF8576C resets to the following starting conditions:
• All backplane and segment outputs are set to V
DD
• The selected drive mode is 1:4 multiplex with
1
⁄
3
bias
• Blinking is switched off
• Input and output bank selectors are reset
• The I
2
C-bus interface is initialized
• The data pointer and the subaddress counter are cleared
Remark: Do not transfer data on the I
2
C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
The full-scale LCD voltage (V
oper
) is obtained from V
DD
V
LCD
. The LCD voltage may be
temperature compensated externally through the V
LCD
supply to pin V
LCD
.
Fractional LCD biasing voltages are obtained from an internal voltage divider comprising
three series resistors connected between V
DD
and V
LCD
. The center resistor can be
switched out of the circuit to provide a
1
⁄
2
bias voltage level for the 1:2 multiplex
configuration.
Fig 6. Typical system configuration
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