PCF8576C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 13 — 16 December 2013 26 of 62
NXP Semiconductors
PCF8576C
Universal LCD driver for low multiplex rates
7.16.5 PCF8576C I
2
C-bus controller
The PCF8576C acts as an I
2
C-bus slave receiver. It does not initiate I
2
C-bus transfers or
transmit data to an I
2
C-bus master receiver. The only data output from the PCF8576C are
the acknowledge signals of the selected devices. Device selection depends on the
I
2
C-bus slave address, the transferred command data and the hardware subaddress.
In single device application, the hardware subaddress inputs A0, A1, and A2 are normally
tied to V
SS
which defines the hardware subaddress 0. In multiple device applications
A0, A1, and A2 are tied to V
SS
or V
DD
using a binary coding scheme so that no two
devices with a common I
2
C-bus slave address have the same hardware subaddress.
In the power-saving mode, it is possible that the PCF8576C is not able to keep up with the
highest transmission rates when large amounts of display data are transmitted. If this
situation occurs, the PCF8576C forces the SCL line LOW until its internal operations are
completed. This is known as the clock synchronization feature of the I
2
C-bus and serves
to slow down fast transmitters. Data loss does not occur.
7.16.6 Input filter
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.17 I
2
C-bus protocol
Two I
2
C-bus slave addresses (0111000 and 0111001) are reserved for the PCF8576C.
The least significant bit of the slave address that a PCF8576C responds to is defined by
the level tied at its input SA0. Therefore, two types of PCF8576C can be distinguished on
the same I
2
C-bus which allows:
• Up to 16 PCF8576Cs on the same I
2
C-bus for very large LCD applications.
• The use of two types of LCD multiplexes on the same I
2
C-bus.
The I
2
C-bus protocol is shown in Figure 19. The sequence is initiated with a START
condition (S) from the I
2
C-bus master which is followed by one of the two PCF8576C
slave addresses available. All PCF8576Cs with the corresponding SA0 level acknowledge
in parallel with the slave address but all PCF8576Cs with the alternative SA0 level ignore
the whole I
2
C-bus transfer.
After acknowledgement, one or more command bytes follow which define the status of the
addressed PCF8576Cs.
The last command byte is tagged with a cleared most significant bit, the continuation bit C.
The command bytes are also acknowledged by all addressed PCF8576Cs on the bus.
After the last command byte, a series of display data bytes may follow. These display
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data is directed to the intended PCF8576C device. The acknowledgement after
each byte is made only by the (A0, A1, and A2) addressed PCF8576C. After the last
display byte, the I
2
C-bus master issues a STOP condition (P).
