DAC1405D650 5 © IDT 2012. All rights reserved.
Product data sheet Rev. 05 — 2 July 2012 10 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
Clock inputs (CLKP and CLKN)
[2]
V
i
input voltage CLKP; or CLKN V
gpd
<50mV C
[3]
825 - 1575 mV
V
idth
input differential
threshold voltage
V
gpd
< 50 mV C
[3]
100 - +100 mV
R
i
input resistance D - 10 - M
C
i
input capacitance D - 0.5 - pF
Digital inputs (I0 to I13, Q0 to Q13)
V
IL
LOW-level input voltage C GNDIO - 1.0 V
V
IH
HIGH-level input
voltage
C2.3-V
DD(IO)(3V3)
V
I
IL
LOW-level input current V
IL
= 1.0 V I - 60 - A
I
IH
HIGH-level input
current
V
IH
= 2.3 V I - 80 - A
Digital inputs (SDO, SDIO, SCLK, SCS_N and RESET_N)
V
IL
LOW-level input voltage C GNDIO - 1.0 V
V
IH
HIGH-level input
voltage
C2.3-V
DD(IO)(3V3)
V
I
IL
LOW-level input current V
IL
= 1.0 V I - 20 - nA
I
IH
HIGH-level input
current
V
IH
= 2.3 V I - 20 - nA
Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN)
I
O(fs)
full-scale output current register value = 00h C - 1.6 - mA
default register C - 20 - mA
V
O
output voltage compliance range C 1.8 - V
DDA(3V3)
V
R
o
output resistance D - 250 - k
C
o
output capacitance D - 3 - pF
N
DAC(mono)
DAC monotonicity guaranteed D - 8 - bit
E
O
offset error variation C - 6 - ppm/C
E
G
gain error variation C - 18 - ppm/C
Reference voltage output (GAPOUT)
V
O(ref)
reference output
voltage
T
amb
= 25 C I 1.24 1.29 1.34 V
V
O(ref)
reference output
voltage variation
C-117- ppm/C
I
O(ref)
reference output
current
external voltage 1.25 V D - 40 - A
Table 5. Characteristics …continued
V
DDA(1V8)
= V
DDD(1V8)
= 1.8 V; V
DDA(3V3)
= V
DD(IO)(3V3)
= 3.3 V; AGND, DGND and GNDIO shorted together; T
amb
=
40
C to
+85
C; typical values measured at T
amb
= 25
C; R
L
= 50
; I
O(fs)
= 20 mA; maximum sample rate; PLL on unless otherwise
specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
DAC1405D650 5 © IDT 2012. All rights reserved.
Product data sheet Rev. 05 — 2 July 2012 11 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)
I
O(aux)
auxiliary output current differential outputs I - 2.2 - mA
V
O(aux)
auxiliary output voltage compliance range C 0 - 2 V
N
DAC(aux)mono
auxiliary DAC
monotonicity
guaranteed D - 10 - bit
Input timing (see Figure 10)
f
data
data rate Dual-port mode input C - - 160 MHz
t
w(CLK)
CLK pulse width C 1.5 - T
data
1.5 ns
t
h(i)
input hold time C 1.1 - - ns
t
su(i)
input set-up time C 1.1 - - ns
Output timing
f
s
sampling frequency C - - 650 Msps
t
s
settling time to 0.5 LSB D - 20 - ns
NCO frequency range; f
s
= 640 Msps
f
NCO
NCO frequency register value = 00000000h D - 0 - MHz
register value = FFFFFFFFh D - 640 - MHz
f
step
step frequency D - 0.149 - Hz
Low-power NCO frequency range; f
DAC
= 640 MHz
f
NCO
NCO frequency register value = 00000000h D - 0 - MHz
register value = F8000000h D - 620 - MHz
f
step
step frequency D - 20 - MHz
Dynamic performance; PLL on
SFDR spurious-free dynamic
range
f
data
= 80 MHz; f
s
=320 Msps; BW=f
data
/ 2
f
o
= 35 MHz at 0 dBFS C - 84 - dBc
f
data
= 80 MHz; f
s
=640 Msps; BW=f
data
/ 2
f
o
= 4 MHz at 0 dBFS I - 77 - dBc
f
o
= 19 MHz at 0 dBFS I - 76 - dBc
f
data
= 160 MHz; f
s
=640 Msps; BW=f
data
/ 2
f
o
= 70 MHz at 0 dBFS C - 84 - dBc
SFDR
RBW
restricted bandwidth
spurious-free dynamic
range
f
s
= 640 Msps; f
o
= 96 MHz at 0 dBFS
2.51 MHz f
offset
2.71 MHz;
B= 30 kHz
I-93 86 dBc
2.71 MHz f
offset
3.51 MHz;
B= 30 kHz
I-92 - dBc
3.51 MHz f
offset
4 MHz;
B=30 kHz
I 93 88 dBc
4 MHz f
offset
40 MHz;
B=1MHz
I-85 72 dBc
Table 5. Characteristics
…continued
V
DDA(1V8)
= V
DDD(1V8)
= 1.8 V; V
DDA(3V3)
= V
DD(IO)(3V3)
= 3.3 V; AGND, DGND and GNDIO shorted together; T
amb
=
40
C to
+85
C; typical values measured at T
amb
= 25
C; R
L
= 50
; I
O(fs)
= 20 mA; maximum sample rate; PLL on unless otherwise
specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
DAC1405D650 5 © IDT 2012. All rights reserved.
Product data sheet Rev. 05 — 2 July 2012 12 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2] CLKP and CLKN inputs are at differential LVDS levels. An external differential resistor with a value of between 80 and 120 should
be connected across the pins (see Figure 8).
[3] V
gpd
represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance
and the inductance between the receiver and the driver circuit ground voltages.
[4] IMD3 rejection with 6 dBFS/tone.
IMD3 third-order
intermodulation
distortion
f
o1
=49MHz; f
o2
=51MHz;
fs = 320 Msps; 4 interpolation
C
[4]
-82- dBc
f
o1
=95MHz; f
o2
=97MHz;
fs = 320 Msps; 4 interpolation
C
[4]
-80- dBc
f
o1
=95MHz; f
o2
=97MHz;
fs = 640 Msps; 8 interpolation
I
[4]
67 80 - dBc
f
o1
= 152 MHz; f
o2
=154MHz;
fs = 640 Msps; 8 interpolation
C
[4]
-77- dBc
ACPR adjacent channel power
ratio
f
data
=76.8MHz; f
s
= 614.4 Msps; f
o
=96MHz
1 carrier; BW = 5 MHz I - 72 - dB
2 carriers; BW = 10 MHz C - 71 - dB
4 carriers; BW = 20 MHz C - 69 - dB
f
data
= 153.6 MHz; f
s
= 614.4 Msps; f
o
=115.2MHz
1 carrier; BW = 5 MHz C - 70 - dB
2 carriers; BW = 10 MHz C - 70 - dB
4 carriers; BW = 20 MHz C - 67 - dB
f
data
= 153.6 MHz; f
s
= 614.4 Msps; f
o
= 153.6 MHz
1 carrier; BW = 5 MHz C - 69 - dB
2 carriers; BW = 10 MHz C - 69 - dB
4 carriers; BW = 20 MHz C - 66 - dB
NSD noise spectral density f
s
= 640 Msps; 8 interpolation; f
o
= 19 MHz at 0 dBFS
noise shaper disable C - 154 - dBm/Hz
noise shaper enable C - 157 - dBm/Hz
Table 5. Characteristics
…continued
V
DDA(1V8)
= V
DDD(1V8)
= 1.8 V; V
DDA(3V3)
= V
DD(IO)(3V3)
= 3.3 V; AGND, DGND and GNDIO shorted together; T
amb
=
40
C to
+85
C; typical values measured at T
amb
= 25
C; R
L
= 50
; I
O(fs)
= 20 mA; maximum sample rate; PLL on unless otherwise
specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit

DAC1405D650HW-C1

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Description:
IC DAC 14BIT A-OUT 100HTQFP
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