DAC1405D650 5 © IDT 2012. All rights reserved.
Product data sheet Rev. 05 — 2 July 2012 10 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
Clock inputs (CLKP and CLKN)
[2]
V
i
input voltage CLKP; or CLKN V
gpd
<50mV C
[3]
825 - 1575 mV
V
idth
input differential
threshold voltage
V
gpd
< 50 mV C
[3]
100 - +100 mV
R
i
input resistance D - 10 - M
C
i
input capacitance D - 0.5 - pF
Digital inputs (I0 to I13, Q0 to Q13)
V
IL
LOW-level input voltage C GNDIO - 1.0 V
V
IH
HIGH-level input
voltage
C2.3-V
DD(IO)(3V3)
V
I
IL
LOW-level input current V
IL
= 1.0 V I - 60 - A
I
IH
HIGH-level input
current
V
IH
= 2.3 V I - 80 - A
Digital inputs (SDO, SDIO, SCLK, SCS_N and RESET_N)
V
IL
LOW-level input voltage C GNDIO - 1.0 V
V
IH
HIGH-level input
voltage
C2.3-V
DD(IO)(3V3)
V
I
IL
LOW-level input current V
IL
= 1.0 V I - 20 - nA
I
IH
HIGH-level input
current
V
IH
= 2.3 V I - 20 - nA
Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN)
I
O(fs)
full-scale output current register value = 00h C - 1.6 - mA
default register C - 20 - mA
V
O
output voltage compliance range C 1.8 - V
DDA(3V3)
V
R
o
output resistance D - 250 - k
C
o
output capacitance D - 3 - pF
N
DAC(mono)
DAC monotonicity guaranteed D - 8 - bit
E
O
offset error variation C - 6 - ppm/C
E
G
gain error variation C - 18 - ppm/C
Reference voltage output (GAPOUT)
V
O(ref)
reference output
voltage
T
amb
= 25 C I 1.24 1.29 1.34 V
V
O(ref)
reference output
voltage variation
C-117- ppm/C
I
O(ref)
reference output
current
external voltage 1.25 V D - 40 - A
Table 5. Characteristics …continued
V
DDA(1V8)
= V
DDD(1V8)
= 1.8 V; V
DDA(3V3)
= V
DD(IO)(3V3)
= 3.3 V; AGND, DGND and GNDIO shorted together; T
amb
=
40
C to
+85
C; typical values measured at T
amb
= 25
C; R
L
= 50
; I
O(fs)
= 20 mA; maximum sample rate; PLL on unless otherwise
specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit