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DAC1405D650HW-C1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
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DAC1405D650 5 © IDT 2012. All rights reserved.
Product data sheet Rev. 05 — 2 July 2012 16 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
Table 9. Register allocation map
Address Register name R/W Bit definition Default
b7 b6 b5 b4 b3 b2 b1 b0 Bin Hex Dec
0 00h COMMon R/W 3W_SPI SPI_RST CLK_SEL - MODE_
SEL
CODING IC_PD GAP_PD 10000000 80 128
1 01h TXCFG R/W NCO_ON NCO_LP_
SEL
INV_SIN_
SEL
MODULATION[2:0] INTERPOLATION[1:0] 10000111 87 135
2 02h PLLCFG R/W PLL_PD - PLL_DIV_
PD
PLL_DIV[1:0] PLL_PHASE[1:0] PLL_POL 00010000 10 16
3 03h FREQNCO_LSB R/W FREQ_NCO[7:0] 01100110 66 102
4 04h FREQNCO_LISB R/W FREQ_NCO[15:8] 01100110 66 102
5 05h FREQNCO_UISB R/W FREQ_NCO[23:16] 01100110 66 102
6 06h FREQNCO_MSB R/W FREQ_NCO[31:24] 00100110 26 38
7 07h PHINCO_LSB R/W PH_NCO[7:0] 00000000 00 0
8 08h PHINCO_MSB R/W PH_NCO[15:8] 00000000 00 0
9 09h DAC_A_Cfg_1 R/W DAC_A_PD DAC_A_
SLEEP
DAC_A_OFFSET[5:0] 00000000 00 0
10 0Ah DAC_A_Cfg_2 R/W DAC_A_GAIN_
COARSE[1:0]
DAC_A_GAIN_FINE[5:0] 01000000 40 64
11 0Bh DAC_A_Cfg_3 R/W DAC_A_GAIN_
COARSE[3:2]
DAC_A_OFFSET[11:6] 11000000 C0 192
12 0Ch DAC_B_Cfg_1 R/W DAC_B_PD DAC_B_
SLEEP
DAC_B_OFFSET[5:0] 00000000 00 0
13 0Dh DAC_B_Cfg_2 R/W DAC_B_GAIN_
COARSE[1:0]
DAC_B_GAIN_FINE[5:0] 01000000 40 64
14 0Eh DAC_B_Cfg_3 R/W DAC_B_GAIN_
COARSE[3:2]
DAC_B_OFFSET[11:6] 11000000 C0 192
15 0Fh DAC_Cfg R/W - - - - - - MINUS_
3DB
NOISE_
SHPER
00000000 00 0
26 1Ah DAC_A_Aux_MSB R/W AUX_A[9:2] 10000000 80 128
27 1Bh DAC_A_Aux_LSB R/W AUX_A_PD - - - - - AUX_A[1:0] 00000000 00 0
28 1Ch DAC_B_Aux_MSB R/W AUX_B[9:2] 10000000 80 128
29 1Dh DAC_B_Aux_LSB R/W AUX_B_PD - - - - - AUX_B[1:0] 00000000 00 0
DAC1405D650 5 © IDT 2012. All rights reserved.
Product data sheet Rev. 05 — 2 July 2012 17 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
10.2.4 Registers detailed description
Please refer to Table 9 for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 10. COMMon register (address 00h) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
7 3W_SPI R/W serial interface bus type
0 4 wire SPI
1 3 wire SPI
6 SPI_RST R/W serial interface reset
0no reset
1 performs a reset on all registers except 0x00
5 CLK_SEL R/W data input latch
0 at CLK rising edge
1 at CLK falling edge
3 MODE_SEL R/W input data mode
0 dual port
1 interleaved
2 CODING R/W coding
0 binary
1 two’s compliment
1 IC_PD R/W power-down
0 disabled
1 all circuits (digital and analog, except SPI)
are switched off
0 GAP_PD R/W internal bandgap power-down
0 power-down disabled
1 internal bandgap references are switched off
Table 11. TXCFG register (address 01h) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
7 NCO_ON R/W NCO
0 disabled (the NCO phase is reset to 0)
1 enabled
6 NCO_LP_SEL R/W low-power NCO
0 disabled
1 NCO frequency and phase given by the five
MSBs of the registers 06h and 08h
respectively
5 INV_SIN_SEL R/W x / (sin x) function
0 disabled
1 enabled
DAC1405D650 5 © IDT 2012. All rights reserved.
Product data sheet Rev. 05 — 2 July 2012 18 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
4 to 2 MODULATION[2:0] R/W modulation
000 dual DAC: no modulation
001 positive upper single sideband
up-conversion
010 positive lower single sideband up-conversion
011 negative upper single sideband
up-conversion
100 negative lower single sideband up-conversion
1 to 0 INTERPOLATION[1:0] R/W interpolation
01 2
10 4
11 8
Table 12. PLLCFG register (address 02h) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
7 PLL_PD R/W PLL
0 switched on
1 switched off
6 - R/W undefined
5 PLL_DIV_PD R/W PLL divider
0 switched on
1 switched off
4 to 3 PLL_DIV[1:0] R/W PLL divider factor
00 2
01 4
10 8
2 to 1 PLL_PHASE[1:0] R/W PLL phase shift of f
s
00 0
01 120
10 240
0 PLL_POL R/W clock edge of DAC (f
s
)
0 normal
1 inverted
Table 13. FREQNCO_LSB register (address 03h) bit description
Bit Symbol Access Value Description
7 to 0 FREQ_NCO[7:0] R/W - lower 8-bits for the NCO frequency setting
Table 11. TXCFG register (address 01h) bit description …continued
Default settings are shown highlighted.
Bit Symbol Access Value Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41

DAC1405D650HW-C1

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IC DAC 14BIT A-OUT 100HTQFP
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