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DAC1405D650HW-C1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
DAC1405D650 5 © IDT 2012. All rights reserved.
Product data sheet Rev. 05 — 2 July 2012 19 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
Table 14. FREQNCO_LISB register (address 04h) bit description
Bit Symbol Access Value Description
7 to 0 FREQ_NCO[15:8] R/W - lower intermediate 8-bits for the NCO
frequency setting
Table 15. FREQNCO_UISB register (address 05h) bit description
Bit Symbol Access Value Description
7 to 0 FREQ_NCO[23:16] R/W - upper intermediate 8-bits for the NCO
frequency setting
Table 16. FREQNCO_MSB register (address 06h) bit description
Bit Symbol Access Value Description
7 to 0 FREQ_NCO[31:24] R/W - most significant 8-bits for the NCO frequency
setting
Table 17. PHINCO_LSB register (address 07h) bit description
Bit Symbol Access Value Description
7 to 0 PH_NCO[7:0] R/W - lower 8-bits for the NCO phase setting
Table 18. PHINCO_MSB register (address 08h) bit description
Bit Symbol Access Value Description
7 to 0 PH_NCO[15:8] R/W - most significant 8-bits for the NCO phase setting
Table 19. DAC_A_Cfg_1 register (address 09h) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
7 DAC_A_PD R/W DAC A power
0on
1off
6 DAC_A_SLEEP R/W DAC A Sleep mode
0disabled
1 enabled
5 to 0 DAC_A_OFFSET[5:0] R/W - lower 6-bits for the DAC A offset
Table 20. DAC_A_Cfg_2 register (address 0Ah) bit description
Bit Symbol Access Value Description
7 to 6 DAC_A_GAIN_COARSE[1:0] R/W - least significant 2-bits for the DAC A
gain setting for coarse adjustment
5 to 0 DAC_A_GAIN_FINE[5:0] R/W - lower 6-bits for the DAC A gain setting
for fine adjustment
DAC1405D650 5 © IDT 2012. All rights reserved.
Product data sheet Rev. 05 — 2 July 2012 20 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
Table 21. DAC_A_Cfg_3 register (address 0Bh) bit description
Bit Symbol Access Value Description
7 to 6 DAC_A_GAIN_COARSE[3:2] R/W - most significant 2-bits for the DAC A
gain setting for coarse adjustment
5 to 0 DAC_A_OFFSET[11:6] R/W - most significant 6-bits for the DAC A
offset
Table 22. DAC_B_Cfg_1 register (address 0Ch) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
7 DAC_B_PD R/W DAC B power
0on
1off
6 DAC_B_SLEEP R/W DAC B Sleep mode
0disabled
1 enabled
5 to 0 DAC_B_OFFSET[5:0] R/W lower 6-bits for the DAC B offset
Table 23. DAC_B_Cfg_2 register (address 0Dh) bit description
Bit Symbol Access Value Description
7 to 6 DAC_B_GAIN_COARSE[1:0] R/W - less significant 2-bits for the DAC B
gain setting for coarse adjustment
5 to 0 DAC_B_GAIN_FINE[5:0] R/W - the 6-bits for the DAC B gain setting for
fine adjustment
Table 24. DAC_B_Cfg_3 register (address 0Eh) bit description
Bit Symbol Access Value Description
7 to 6 DAC_B_GAIN_COARSE[3:2] R/W - most significant 2-bits for the DAC B
gain setting for coarse adjustment
5 to 0 DAC_B_OFFSET[11:6] R/W - most significant 6-bits for the DAC B
offset
Table 25. DAC_Cfg register (address 0Fh) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
1 MINUS_3DB R/W NCO gain
0unity
1 3 dB
0 NOISE_SHPER R/W noise shaper
0 disabled
1 enabled
Table 26. DAC_A_Aux_MSB register (address 1Ah) bit description
Bit Symbol Access Value Description
7 to 0 AUX_A[9:2] R/W - most significant 8-bits for the auxiliary DAC A
DAC1405D650 5 © IDT 2012. All rights reserved.
Product data sheet Rev. 05 — 2 July 2012 21 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
10.3 Input data
The setting applied to MODE_SEL (register 00h[3]; see Table 10 on page 17) and it
defines whether the DAC1405D650 operates in the Dual-port mode or in the Interleaved
mode (see Table 30).
10.3.1 Dual-port mode
The data input for Dual-port mode operation is shown in Figure 5 “Dual-port mode”. Each
DAC has its own independent data input. The data enters the input latch on the rising
edge of the internal clock signal and is transferred to the DAC latch.
Table 27. DAC_A_Aux_LSB register (address 1Bh) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
7 AUX_A_PD R/W auxiliary DAC A power
0on
1off
1 to 0 AUX_A[1:0] R/W lower 2-bits for the auxiliary DAC A
Table 28. DAC_B_Aux_MSB register (address 1Ch) bit description
Bit Symbol Access Value Description
7 to 0 AUX_B[9:2] R/W - most significant 8-bits for the auxiliary
DAC B
Table 29. DAC_B_Aux_LSB register (address 1Dh) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
7 AUX_B_PD R/W auxiliary DAC B power
0on
1off
1 to 0 AUX_B[1:0] R/W lower 2-bits for the auxiliary DAC B
Table 30. Mode selection
Bit 3 setting Function I13 to I0 Q13 to Q0 Pin 41
0 Dual port mode active active Q13
1 Interleaved mode active off SELIQ
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41

DAC1405D650HW-C1

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IC DAC 14BIT A-OUT 100HTQFP
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