DAC1405D650HW-C1 Datasheet DAC1405D650-DB, DAC1405D650HW-C18, DAC1405D650HW-C1 | P25-P27

Product data sheet Rev. 05 — 2 July 2012 25 of 41

Integrated Device Technology

DAC1405D650

Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating

The settings applied to PLL_PHASE[1:0] (register 02h[2:1]) and PLL_POL

(register 02h[0]), allows adjustment of the phase and polarity of the sampling clock. This

occurs at the input of the DAC core and depends mainly on the sampling frequency. Some

examples are given in Table 32 “Sample clock phase and polarity examples”.

10.6 FIR filters

The DAC1405D650 integrates three selectable Finite Impulse Response (FIR) filters

which allows the device to use 2, 4 or 8 interpolation rates.

All three interpolation filters have a stop-band attenuation of at least 80 dBc and a

pass-band ripple of less than 0.0005 dB.

The coefficients of the interpolation filters are given in Table 33 “Interpolation filter

coefficients”.

Table 32. Sample clock phase and polarity examples

Mode Input data rate

(MHz)

Interpolation Update rate

(Msps)

PLL_PHASE

[1:0]

PLL_POL

Dual Port 80 2 160 01 1

Dual Port 80 4 320 01 0

Dual Port 80 8 640 01 1

Interleaved 160 2 160 01 1

Interleaved 160 4 320 01 0

Interleaved 160 8 640 01 1

Table 33. Interpolation filter coefficients

First interpolation filter Second interpolation filter Third interpolation filter

Lower Upper Value Lower Upper Value Lower Upper Value

H(1) H(55) 4 H(1) H(23) 2 H(1) H(15) 39

H(2) H(54) 0 H(2) H(22) 0 H(2) H(14) 0

H(3) H(53) 13 H(3) H(21) 17 H(3) H(13) 273

H(4) H(52) 0 H(4) H(20) 0 H(4) H(12) 0

H(5) H(51) 34 H(5) H(19) 75 H(5) H(11) 1102

H(6) H(50) 0 H(6) H(18) 0 H(6) H(10) 0

H(7) H(49) 72 H(7) H(17) 238 H(7) H(9) 4964

H(8) H(48) 0 H(8) H(16) 0 H(8) - 8192

H(9) H(47) 138 H(9) H(15) 660 - - -

H(10) H(46) 0 H(10) H(14) 0 - - -

H(11) H(45) 245 H(11) H(13) 2530 - - -

H(12) H(44) 0 H(12) - 4096 - - -

H(13) H(43) 408------

H(14)H(42)0------

H(15) H(41) 650 - - - - - -

H(16)H(40)0------

H(17) H(39) 1003------

H(18)H(38)0------

Product data sheet Rev. 05 — 2 July 2012 26 of 41

Integrated Device Technology

DAC1405D650

Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating

10.7 Quadrature modulator and Numerically Controlled Oscillator (NCO)

The quadrature modulator allows the 14-bit I and Q data to be mixed with the carrier

signal generated by the NCO.

The frequency of the NCO is programmed over 32-bit and allows the sign of the sine

component to be inverted in order to operate positive or negative, lower or upper single

sideband up-conversion.

10.7.1 NCO in 32-bit

When using the NCO, the frequency can be set by the four registers FREQNCO_LSB,

FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits.

The frequency for the NCO in 32-bit is calculated as follows:

(1)

where M is the decimal representation of FREQ_NCO[31:0].

The phase of the NCO can be set from 0 to 360 by both registers PHINCO_LSB and

PHINCO_MSB over 16 bits.

The default setting is f

NCO

= 96 MHz when f

= 640 Msps and the default phase is 0.

10.7.2 Low-power NCO

When using the low-power NCO, the frequency can be set by the 5 MSB of register

FREQNCO_MSB.

The frequency for the low-power NCO is calculated as follows:

(2)

where M is the decimal representation of FREQ_NCO[31:27].

H(19) H(37) 1521 - - - - - -

H(20)H(36)0------

H(21) H(35) 2315------

H(22)H(34)0------

H(23) H(33) 3671 - - - - - -

H(24)H(32)0------

H(25) H(31) 6642------

H(26)H(30)0------

H(27) H(29) 20756 - - - - - -

H(28) 32768------

Table 33. Interpolation filter coefficients

…continued

First interpolation filter Second interpolation filter Third interpolation filter

Lower Upper Value Lower Upper Value Lower Upper Value

NCO



--------------

NCO



--------------

Product data sheet Rev. 05 — 2 July 2012 27 of 41

Integrated Device Technology

DAC1405D650

Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating

The phase of the low-power NCO can be set by the 5 MSB of the register PHINCO_MSB.

10.7.3 Minus 3dB

During normal use, a full-scale pattern will also be full scale at the output of the DAC.

Nevertheless, when the I and Q data are simultaneously close to full scale, some clipping

can occur and the Minus_3dB function can be used to reduce the gain by 3 dB in the

modulator. This is to keep a full-scale range at the output of the DAC without added

interferers.

10.8 x / (sin x)

Due to the roll-off effect of the DAC, a selectable FIR filter is inserted to compensate for

the (sin x) / x effect. This filter introduces a DC loss of 3.4 dB. The coefficients are

represented in Table 34 “Inversion filter coefficients”.

10.9 DAC transfer function

The full-scale output current for each DAC is the sum of the two complementary current

outputs:

(3)

The output current depends on the digital input data:

(4)

(5)

The setting applied to CODING (register 00h[2]; see Table 9 “Register allocation map”)

defines whether the DAC1405D650 operates with a binary input or a two’s complement

input.

Table 35 “DAC transfer function” shows the output current as a function of the input data,

when I

O(fs)

= 20 mA.

Table 34. Inversion filter coefficients

First interpolation filter

Lower Upper Value

H(1) H(9) 2

H(2) H(8) 4

H(3) H(7) 10

H(4) H(6) 35

H(5) - 401

Ofs

IOUTP

IOUTN

IOUTP

Ofs

DATA

16383

----------------





=

IOUTN

Ofs

16383 DATA–

16383

-------------------------------------





=

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DAC1405D650HW-C1

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