DAC1405D650 5 © IDT 2012. All rights reserved.
Product data sheet Rev. 05 — 2 July 2012 24 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
10.5 Timing
The DAC1405D650 can operate at an update rate (f
s
) of up to 650 Msps and with an input
data rate (f
data
) of up to 160 MHz. The input timing is shown in Figure 10 “Input timing
diagram”.
The typical performances are measured at 50 % duty cycle but any timing within the limits
of the characteristics will not alter the performance.
In Table 31 “Frequencies”, the links between internal and external clocking are defined.
The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see Table 9 “Register allocation
map”) allows the frequency between the digital part and the DAC core to be adjusted.
Fig 9. Interfacing CML to LVDS
001aah020
55 Ω
55 Ω
1.1 kΩ
2.2 kΩ
100 nF
CML
100 nF
100 nF
CLKINP
LVDS
CLKINN
AGND
V
DDA(1V8)
1 kΩZ
diff
= 100 Ω
Fig 10. Input timing diagram
Table 31. Frequencies
Mode CLK input
(MHz)
Input data rate
(MHz)
Interpolation Update rate
(Msps)
PLL_DIV[1:0]
Dual Port 160 160 2 320 01 (/4)
Dual Port 160 160 4 640 01 (/4)
Dual Port 80 80 8 640 10 (/8)
Interleaved 320 320 2 320 00 (/2)
Interleaved 320 320 4 640 00 (/2)
Interleaved 160 160 8 640 01 (/4)
001aaj815
N
t
su(i)
90 %
50 %
90 %
In/Qn
CLK
(CLKP-CLKN)
t
h(i)
t
w(CLK)
N + 1 N + 2
