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DAC1405D650HW-C1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
DAC1405D650 5 © IDT 2012. All rights reserved.
Product data sheet Rev. 05 — 2 July 2012 28 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
10.10 Full-scale current
10.10.1 Regulation
The DAC1405D650 reference circuitry integrates an internal bandgap reference voltage
which delivers a 1.29 V reference to the GAPOUT pin. It is recommended to decouple pin
GAPOUT using a 100 nF capacitor.
The reference current is generated via an external resistor of 953 (1 %) connected to
pin VIRES. A control amplifier sets the appropriate full-scale current (I
O(fs)
) for both DACs
(see Figure 11 “Internal reference configuration”).
This configuration is optimum for temperature drift compensation because the bandgap
reference voltage can be matched to the voltage across the feedback resistor.
The DAC current can also be set by applying an external reference voltage to the
non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage
with GAP_PD (register 00h[0]; see Table 10 “COMMon register (address 00h) bit
description”).
10.10.2 Full-scale current adjustment
The default full-scale current (I
O(fs)
) is 20 mA but further adjustments can be made by the
user to both DACs independently via the serial interface from 1.6 mA to 22 mA, +/- 10 %.
The settings applied to DAC_A_GAIN_COARSE[3:0] (register 0Ah; see Table 20
“DAC_A_Cfg_2 register (address 0Ah) bit description” and register 0Bh; see Table 21
“DAC_A_Cfg_3 register (address 0Bh) bit description”) and to DAC_B_GAIN
Table 35. DAC transfer function
Data I13/Q13 to I0/Q0 IOUTP IOUTN
Binary Two’s complement
0 00 0000 0000 0000 10 0000 0000 0000 0 mA 20 mA
... ... ... ... ...
8192 10 0000 0000 0000 00 0000 0000 0000 10 mA 10 mA
... ... ... ... ...
16383 11 1111 1111 1111 01 1111 1111 1111 20 mA 0 mA
Fig 11. Internal reference configuration
aaa-002266
REF.
BANDGAP
GAPOUT
V
DDA(1V8)
VIRES
DAC
CURRENT
SOURCES
ARRAY
A
GND
A
GND
100 nF
953 Ω
(1 %)
100
kΩ
DAC1405D650 5 © IDT 2012. All rights reserved.
Product data sheet Rev. 05 — 2 July 2012 29 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
COARSE[3:0] (register 0Dh; see Table 23 “DAC_B_Cfg_2 register (address 0Dh) bit
description” and register 0Eh; see Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit
description”) define the coarse variation of the full-scale current (see Table 36 “I
O(fs)
coarse adjustment”).
The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see Table 20
“DAC_A_Cfg_2 register (address 0Ah) bit description”) and to DAC_B_GAIN_FINE[5:0]
(register 0Dh; see Table 23 “DAC_B_Cfg_2 register (address 0Dh) bit description”) define
the fine variation of the full-scale current (see Table 37 “I
O(fs)
fine adjustment”).
The coding of the fine gain adjustment is two’s complement.
Table 36. I
O(fs)
coarse adjustment
Default settings are shown highlighted.
DAC_GAIN_COARSE[3:0] I
O(fs)
(mA)
Decimal Binary
0 0000 1.6
1 0001 3.0
2 0010 4.4
3 0011 5.8
4 0100 7.2
5 0101 8.6
6011010.0
7 0111 11.4
8 1000 12.8
9 1001 14.2
10 1010 15.6
11 1011 17.0
12 1100 18.5
13 1101 20.0
14 1110 21.0
15 1111 22.0
Table 37. I
O(fs)
fine adjustment
Default settings are shown highlighted.
DAC_GAIN_FINE[5:0] Delta I
O(fs)
Decimal Two’s complement
32 10 0000 10 %
... ... ...
0 00 0000 0
... ... ...
31 01 1111 +10 %
DAC1405D650 5 © IDT 2012. All rights reserved.
Product data sheet Rev. 05 — 2 July 2012 30 of 41
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
10.11 Digital offset adjustment
When the DAC1405D650 analog output is DC connected to the next stage, the digital
offset correction can be used to adjust the common mode level at the output of the DAC. It
adds an offset at the end of the digital part, just before the DAC.
The settings applied to DAC_A_OFFSET[11:0] (register 09h; see Table 19
“DAC_A_Cfg_1 register (address 09h) bit description” and register 0Bh; see Table 21
“DAC_A_Cfg_3 register (address 0Bh) bit description”) and to “DAC_B_OFFSET[11:0]”
(register 0Ch; see Table 22 “DAC_B_Cfg_1 register (address 0Ch) bit description” and
register 0Eh; see Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit description”) define
the range of variation of the digital offset (see Table 38 “Digital offset adjustment”).
10.12 Analog output
The DAC1405D650 has two output channels each of which produces two complementary
current outputs. These allow the even-order harmonics and noise to be reduced. The pins
are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected via a
load resistor R
L
to the 3.3 V analog power supply (V
DDA(3V3)
).
For the equivalent analog output circuit of one DAC, refer to Figure 12 “Equivalent analog
output circuit (one DAC)”. This circuit consists of a parallel combination of NMOS current
sources, and their associated switches, for each segment.
Table 38. Digital offset adjustment
Default settings are shown highlighted.
DAC_OFFSET[11:0] Offset applied
Decimal Two’s complement
2048 1000 0000 0000 4096
2047 1000 0000 0001 4094
... ... ...
1 1111 1111 1111 2
0 0000 0000 0000 0
+1 0000 0000 0001 +2
... ... ...
2046 0111 1111 1110 +4092
2047 0111 1111 1111 +4094
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DAC1405D650HW-C1

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IC DAC 14BIT A-OUT 100HTQFP
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