TDA19977A_TDA19977B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 7 August 2008 2 of 40
NXP Semiconductors
TDA19977A; TDA19977B
Triple input HDMI receiver interface with digital processing
on the ITU-R BT.656 format. The device can adjust the output timing of the video port by
altering the values of t
su(Q)
and t
h(Q)
. In addition, all settings are controllable using the
I
2
C-bus.
2. Features
n Complies with the HDMI 1.3a, DVI 1.0, CEA-861-D and HDCP (TDA19977A only)
1.2 standards
n Three independent HDMI inputs, up to the HDMI frequency of 235 MHz
n Embedded auto-adaptive equalizer on all HDMI links
n EDID memory: 253 shared bytes and three bytes dedicated to each HDMI input
n Supports color depth processing (8-bit, 10-bit or 12-bit per color)
n Color gamut metadata packet with interrupt on each update, readable via the I
2
C-bus
n Up to four S/PDIF or I
2
S-bus outputs (eight channels) at a sampling rate up to 192 kHz
with IEC 60958/IEC 61937 stream
n HBR audio stream up to 768 kHz with four demultiplexed S/PDIF or I
2
S-bus outputs
n HBR streams (e.g. DTS-HD master audio and Dolby TrueHD up to eight channels due
to HBR packet for stream with a frame rate up to 768 kHz) support
n DSD and DST audio stream up to six DSD channels output for SACD with DST audio
packet support
n Channel status decoder supports multi-channel reception
n Improved audio clock generation using an external reference clock
n System/master clock output (128/256/512 × f
s
) enables the use of the UDA1334BTS
n The HDMI interface supports:
u All HDTV formats up to 1920 × 1080p at 50/60 Hz and WUXGA (1920 × 1200p at
60 Hz) with support for reduced blanking
u PC formats up to UXGA (1600 × 1200p at 60 Hz)
n Embedded oscillator (an external crystal can be used)
n Frame and field detection for interlaced video signal
n Sync timing measurements for format recognition
n Improved system for measurements of blanking and video active area allowing an
accurate recognition of PC and TV formats
n HDCP (TDA19977A only) with repeater capability
n Embedded non-volatile memory storage of HDCP (TDA19977A only) keys
n Programmable color space input signal conversion from RGB-to-YCbCr or
YCbCr-to-RGB
n Output formats: RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 semi-planar based on the
ITU-R BT.601 standard and YCbCr 4:2:2 ITU-R BT.656
n 8-bit, 10-bit or 12-bit output formats selectable using the I
2
C-bus (8-bit and 10-bit only
in 4:4:4 format)
n I
2
C-bus adjustable timing of video port (t
su(Q)
and t
h(Q)
)
n Downsampling-by-two with selectable filters on Cb and Cr channels in 4:2:2 mode
n Internal video and audio pattern generator
n Controllable using the I
2
C-bus; 5 V tolerant and bit rate up to 400 kbit/s
n DDC-bus inputs 5 V tolerant and bit rate up to 400 kbit/s
n LV-TTL outputs
