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TDA19977AHV/15,557

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
TDA19977A_TDA19977B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 7 August 2008 19 of 40
NXP Semiconductors
TDA19977A; TDA19977B
Triple input HDMI receiver interface with digital processing
I
DDC(1V8)
core supply current (1.8 V) 720p at 60 Hz
[1]
- 148 - mA
1080p at 60 Hz
[1]
- 283 - mA
1080p at 60 Hz;
Deep Color mode 12-bit
[1]
- 453 - mA
∆V
DD(3V3-3V3)
supply voltage difference between
two 3.3 V supplies
start-up and established
conditions
−100 - +100 mV
∆V
DD(1V8-1V8)
supply voltage difference between
two 1.8 V supplies
start-up and established
conditions
−100 - +100 mV
P power dissipation active mode
[1]
720p at 60 Hz - 0.75 - W
1080p at 60 Hz - 1.13 - W
1080p at 60 Hz;
Deep Color mode 12-bit
- 1.63 - W
P
cons
power consumption Power-down mode
pin PD = HIGH - 1 - mW
I
2
C-bus; EDID and HDCP
[2]
memory power-up
-4 - mW
I
2
C-bus; EDID; activity
detection and HDCP
[2]
memory power-up
- 150 - mW
Clock timing output: pins VCLK, ACLK and SYSCLK
f
clk(max)
maximum clock frequency pin VCLK 165 - - MHz
pin ACLK 25 - - MHz
pin SYSCLK 50 - - MHz
δ
clk
clock duty cycle pin VCLK - 50 - %
pin ACLK - 50 - %
pin SYSCLK - 50 - %
Timing output: pins VP[29:0]; f
s
= 165 MHz; C
L
= 10 pF; see Figure 5
t
su(Q)
data output set-up time CLKOUT_DEL = 0;
CLKOUT_TOG = 0
1.50 - - ns
CLKOUT_DEL = 1;
CLKOUT_TOG = 1;
CLKOUT_DEL_SEL[2:0] = 4
0.40 - - ns
t
h(Q)
data output hold time CLKOUT_DEL = 0;
CLKOUT_TOG = 0
0.80 - - ns
CLKOUT_DEL = 1;
CLKOUT_TOG = 1;
CLKOUT_DEL_SEL[2:0] = 4
2.00 - - ns
t
d(pipe)
pipeline delay time from inputs to outputs; all modes;
clock interval
-80× T
clk
-
Timing output: pins AP[5:0] with respect to ACLK; f
clk
= 12.288 MHz; C
L
= 10 pF; see Figure 6
t
su(Q)
data output set-up time 69 - - ns
t
h(Q)
data output hold time 2 - - ns
Table 10. Characteristics
…continued
T
amb
=0
°
Cto70
°
C; typical values measured at T
amb
=25
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
TDA19977A_TDA19977B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 7 August 2008 20 of 40
NXP Semiconductors
TDA19977A; TDA19977B
Triple input HDMI receiver interface with digital processing
[1] At 30 % activity on video port output.
[2] HDCP decoding is only supported by TDA19977A.
[3] In high-impedance state, the output buffer is set to repeater mode recopying the input logic state with a small current. The output current
changes from most negative to the most positive value at the triggering level which is internally set to V
DDO(3V3)
/ 2 (e.g. the value of a
pull-up or pull-down resistor must be lower than 18 kΩ to have a stable output value of V
DDO(3V3)
or 0 V).
[4] x = A, B or C.
[5] Fast mode, 5 V tolerant.
[6] 5 V tolerant.
LV-TTL digital outputs: pins VP[29:0], VCLK, AP[5:0], ACLK, DE, HS, VS, HREF, VREF, FREF; C
L
=10pF
V
OL
LOW-level output voltage I
OL
= 2 mA - - 0.4 V
V
OH
HIGH-level output voltage I
OH
= −2 mA 2.4 - - V
I
LOZ
OFF-state output leakage current high-impedance state; V
O
=0V
[3]
-0 - µA
V
O
= V
DDO(3V3)
×
1
⁄
3
10 - 100 µA
V
O
= V
DDO(3V3)
×
2
⁄
3
−100 - −10 µA
V
O
= V
DDO(3V3)
-0 - µA
Digital inputs: pins RXxC+, RXxC−
[4]
V
I(dif)
differential input voltage R
RRX1
=12kΩ±1%;
R
RRX2
=12kΩ±1%
150 - 1200 mV
V
I(cm)
common-mode input voltage 2.735 - 3.475 V
f
clk(max)
maximum clock frequency 235 - - MHz
Digital inputs: pins RXx0+, RXx0−, RXx1+, RXx1−, RXx2+, RXx2−
[4]
V
I(dif)
differential input voltage R
RRX1
=12kΩ±1%;
R
RRX2
=12kΩ±1%
150 - 1200 mV
V
I(cm)
common-mode input voltage 2.735 - 3.475 V
I
2
C-bus: pins SCL and SDA
[5]
f
SCL
SCL clock frequency - - 400 kHz
C
b
capacitive load for each bus line - - 400 pF
C
i
capacitance for each I/O pin - - 10 pF
DDC I
2
C-bus: pins HSCLx, HSDAx
[4][6]
f
SCL
SCL clock frequency standard-mode - - 100 kHz
fast-mode - - 400 kHz
C
i
capacitance for each I/O pin - - 10 pF
Table 10. Characteristics
…continued
T
amb
=0
°
Cto70
°
C; typical values measured at T
amb
=25
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
TDA19977A_TDA19977B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 7 August 2008 21 of 40
NXP Semiconductors
TDA19977A; TDA19977B
Triple input HDMI receiver interface with digital processing
Fig 5. Output timing diagram pin VCLK on pins VP[29:0]
Fig 6. Output timing diagram pin ACLK on pins AP[5:0]
001aah368
VCLK 50 %
2.4 V
0.4 V
VP[29:0]
t
su(Q)
t
h(Q)
001aah369
ACLK 50 %
2.4 V
0.4 V
AP[5:0]
t
su(Q)
t
h(Q)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

TDA19977AHV/15,557

Mfr. #:
Buy TDA19977AHV/15,557
Manufacturer:
NXP Semiconductors
Description:
Bus Receivers TRPL INPUT HDMI 1.3A COMP RECEIVER INTFCE
Lifecycle:
New from this manufacturer.
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