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TDA19977AHV/15,557

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
TDA19977A_TDA19977B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 7 August 2008 10 of 40
NXP Semiconductors
TDA19977A; TDA19977B
Triple input HDMI receiver interface with digital processing
[1] P = power supply; G = ground; I = input; O = output and I/O = input/output.
[2] Connected to the ground of the HDMI receiver (V
SSH
) in normal operation.
[3] HDCP decoding is only supported by TDA19977A.
8. Functional description
The TDA19977A; TDA19977B converts digital data streams input by the HDMI sources
into parallel digital data for use by media and video signal processing integrated circuits
such as NXP Semiconductors’ Nexperia devices for HDTV. Data streams can be decoded
with or without HDCP (TDA19977A only) protection.
Outputs from the TDA19977A; TDA19977B can be RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2
semi-planar format based on the ITU-R BT.601 standard or YCbCr 4:2:2 based on the
ITU-R BT.656 format. Inputs can be both progressive and interlaced formats. The
TDA19977A; TDA19977B comprises a color space conversion block, downsampling filters
and an embedded timing code function. In addition, the HDCP (TDA19977A only)
repeater function enables other HDMI devices to be connected to form an extended “total
application”.
8.1 Software drivers
Software drivers are provided for easy configuration and use of the TDA19977A;
TDA19977B. These drivers can be integrated with a large range of processors, with or
without an operating system. They control activity detection, input selection, video mode
identification, color conversion, Power-down modes, HDCP (TDA19977A only) and
InfoFrame notification.
8.2 HDMI inputs
Control of the three HDMI inputs can be automatic using activity detection or using the
I
2
C-bus. The HDMI receiver inputs are defined by pins RXx0+, RXx0−, RXx1+, RXx1−,
RXx2+, RXx2−, RXxC+, RXxC−, RRXx, HSCLx and HSDAx. In the pin names, x equals A,
B or C (as applicable).
8.3 Termination resistance control
The HDMI receiver input contains a termination resistance control set by an external
resistor connected between pins RRXx and V
DDH(3V3)
. In RRXx, x equals 1 for inputs A
and B or 2 for inputs C and D. Typically, the characteristic impedance is 50 Ω and the
default value of the external terminal control resistor is 12 kΩ± 1 %.
HSCLC 139 I HDMI input C (HDCP
[3]
) DDC-bus serial clock
n.c. 140 I/O not connected
n.c 141 I not connected
V
DDI(3V3)
142 P digital inputs supply voltage; 3.3 V
RRX2 143 I HDMI inputs C and D termination resistance control
V
DDH(1V8)
144 P HDMI receiver supply voltage; 1.8 V
Exposed die pad - G exposed die pad; connect to digital core ground (V
SSC
)
Table 3. Pin description
…continued
Symbol Pin Type
[1]
Description
TDA19977A_TDA19977B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 7 August 2008 11 of 40
NXP Semiconductors
TDA19977A; TDA19977B
Triple input HDMI receiver interface with digital processing
8.4 Equalizer
The auto-adaptive equalizer automatically measures and selects the settings which
provide the best signal quality for each cable. This improves signal quality and enables the
use of cable lengths up to 25 m (laboratory tested, contact NXP for detailed information).
The equalizer is fully automatic and consequently does not need any external control.
8.5 Activity detection
The TDA19977A; TDA19977B uses activity detection to automatically select the active
HDMI input. An internal, fully programmable, frequency filter controls activity detection. It
sees only the activity on the HDMI inputs with a frequency range between f
min
(22.5 MHz)
and f
max
(235 MHz).
This activity detection can generate an interrupt enabling users to manage each HDMI
input.
8.6 High-bandwidth digital content protection (TDA19977A only)
The HDMI receiver also contains the HDCP decryption function. The keys provided by the
OTP non-volatile memory in encrypted format are decrypted and then stored in the HDCP
module. This is particularly suitable for repeater applications. The TDA19977A manages
all HDCP repeater functions based on the HDCP 1.2 specification.
Three DDC-buses HSCLA/HSDAA; HSCLB/HSDAB and HSCLC/HSDAC are integrated
into the HDCP function, one bus for each HDMI input. The DDC-bus connected to the
HDCP block is automatically selected based on the active HDMI input. The unused inputs
are disconnected from the DDC-bus (no acknowledge). No additional CPU processing is
required because the authentication phase and the re-key calculation are fully managed
by the TDA19977A.
8.7 Color depth unpacking
In Deep Color mode, the TDA19977A; TDA19977B receives several fragments of a pixel
group at the HDMI link frequency. This block translates the received pixel group into pixels
at the pixel frequency. This operation is fully automatic and does not need any external
control.
8.8 Derepeater
The HDMI source uses pixel repetition to increase the transmitted pixel clock for
transmitting video formats at native pixel rates below 25 Mpixel/s or to increase the
number of audio sample packets in each line. The derepeater function discards repeated
pixels and divides the clock to reproduce the native video format.
8.9 Upsample
The HDMI source can use YCbCr 4:2:2 pixel encoding which enables the number of bits
allocated per component to be increased up to 12. The upsample function transforms this
12-bit YCbCr 4:2:2 data stream into a 12-bit YCbCr 4:4:4 data stream by repeating or
linearly interpolating the chrominance pixels Cb and Cr.
Upsampling mode is selected using the I
2
C-bus.
TDA19977A_TDA19977B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 7 August 2008 12 of 40
NXP Semiconductors
TDA19977A; TDA19977B
Triple input HDMI receiver interface with digital processing
8.10 Packet extraction
Information sent during the Data Island periods are extracted from the HDMI data stream.
Audio clock regeneration, general control and InfoFrames can be read using the I
2
C-bus
while audio samples are sent to the audio FIFO.
The TDA19977A; TDA19977B can receive the new HDMI 1.3a packets, general control
and color gamut metadata information packets.
In audio applications, the TDA19977A; TDA19977B manages HBR packets for high bit
rate compressed audio streams (IEC 61937), OBA samples and DST packets for OBA
and SACD with DSD and DST audio streams.
The TDA19977A; TDA19977B includes a two channel status decoder supporting
multi-channel reception for audio sample packets. This enables the user to obtain channel
status information from the IEC 60958/IEC 61937 stream such as:
• The audio stream type (non-linear as IEC 61937 or L-PCM as IEC 60958)
• Copyright protection
• Sampling frequency
Refer to
IEC 60958/IEC 61937 specifications
for more details.
An update of each InfoFrame or the channel status content is indicated by a register bit
and the HIGH-to-LOW transition on output pin VAI. This makes CPU polling unnecessary.
8.11 Audio PLL
The TDA19977A; TDA19977B generates a 128/256/512 × f
s
system clock enabling the
use of simple audio DACs without an integrated PLL, such as the UDA1334BTS. The
programming of the audio PLL can be either automatic, using the audio clock regeneration
parameters found in the Data Islands or set manually using the I
2
C-bus.
All standard audio sampling frequencies 32 kHz, 44.1 kHz, 88.2 kHz, 176.4 kHz, 48 kHz,
96 kHz and 192 kHz are accepted by the device.
8.12 Audio formatter
Audio samples can be output in either S/PDIF, I
2
S-bus formats or DSD (SACD). In I
2
S-bus
or S/PDIF modes, up to eight audio channels can be controlled using the audio port pins
(AP0 to AP5). In DSD mode (SACD), up to six audio channels can be controlled using
these pins. The audio port mapping depends on the channel allocation (see Table 4,
Table 5 and Table 6 for detailed information).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

TDA19977AHV/15,557

Mfr. #:
Buy TDA19977AHV/15,557
Manufacturer:
NXP Semiconductors
Description:
Bus Receivers TRPL INPUT HDMI 1.3A COMP RECEIVER INTFCE
Lifecycle:
New from this manufacturer.
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