TDA19977A_TDA19977B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 7 August 2008 26 of 40
NXP Semiconductors
TDA19977A; TDA19977B
Triple input HDMI receiver interface with digital processing
[1] Z = high-impedance; L = LOW-level; depending on bit VPL.
Table 15. Output in 8-bit video port format (register VP_CTRL address = A1h)
Signal RGB
[1]
YCbCr 4:4:4
[1]
YCbCr 4:2:2 semi-planar
[1]
YCbCr 4:2:2 ITU-R BT.656
[1]
VP[29] G[11] Y[11] Y
0
[11] Y
1
[11] Z/L Z/L Z/L Z/L
VP[28] G[10] Y[10] Y
0
[10] Y
1
[10] Z/L Z/L Z/L Z/L
VP[27] G[9] Y[9] Y
0
[9] Y
1
[9] Z/L Z/L Z/L Z/L
VP[26] G[8] Y[8] Y
0
[8] Y
1
[8] Z/L Z/L Z/L Z/L
VP[25] G[7] Y[7] Y
0
[7] Y
1
[7] Z/L Z/L Z/L Z/L
VP[24] G[6] Y[6] Y
0
[6] Y
1
[6] Z/L Z/L Z/L Z/L
VP[23] G[5] Y[5] Y
0
[5] Y
1
[5] Z/L Z/L Z/L Z/L
VP[22] G[4] Y[4] Y
0
[4] Y
1
[4] Z/L Z/L Z/L Z/L
VP[21] R[11] Cr[11] Cb[11] Cr[11] Cb[11] Y
0
[11] Cr[11] Y
1
[11]
VP[20] R[10] Cr[10] Cb[10] Cr[10] Cb[10] Y
0
[10] Cr[10] Y
1
[10]
VP[19] R[9] Cr[9] Cb[9] Cr[9] Cb[9] Y
0
[9] Cr[9] Y
1
[9]
VP[18] R[8] Cr[8] Cb[8] Cr[8] Cb[8] Y
0
[8] Cr[8] Y
1
[8]
VP[17] R[7] Cr[7] Cb[7] Cr[7] Cb[7] Y
0
[7] Cr[7] Y
1
[7]
VP[16] R[6] Cr[6] Cb[6] Cr[6] Cb[6] Y
0
[6] Cr[6] Y
1
[6]
VP[15] R[5] Cr[5] Cb[5] Cr[5] Cb[5] Y
0
[5] Cr[5] Y
1
[5]
VP[14] R[4] Cr[4] Cb[4] Cr[4] Cb[4] Y
0
[4] Cr[4] Y
1
[4]
VP[13] B[11] Cb[11] Z/L Z/L Z/L Z/L Z/L Z/L
VP[12] B[10] Cb[10] Z/L Z/L Z/L Z/L Z/L Z/L
VP[11] B[9] Cb[9] Z/L Z/L Z/L Z/L Z/L Z/L
VP[10] B[8] Cb[8] Z/L Z/L Z/L Z/L Z/L Z/L
VP[9] B[7] Cb[7] Z/L Z/L Z/L Z/L Z/L Z/L
VP[8] B[6] Cb[6] Z/L Z/L Z/L Z/L Z/L Z/L
VP[7] B[5] Cb[5] Z/L Z/L Z/L Z/L Z/L Z/L
VP[6] B[4] Cb[4] Z/L Z/L Z/L Z/L Z/L Z/L
VP[5] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L
VP[4] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L
VP[3] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L
VP[2] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L
VP[1] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L
VP[0] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L
