TDA19977A_TDA19977B_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 7 August 2008 16 of 40
NXP Semiconductors
TDA19977A; TDA19977B
Triple input HDMI receiver interface with digital processing
8.24 Power management
The TDA19977A; TDA19977B can use one of three Power-down modes:
• level 0: full Power-down mode
• level 1: internal EDID memory with I
2
C-bus serial interface active
• level 2: internal EDID memory with I
2
C-bus serial interface and activity detection
enabled
The user can activate these different modes with pin PD or using I
2
C-bus registers:
• level 0: PD pin is HIGH
• level 1: settings defined in the I
2
C-bus registers
• level 2: with settings defined in the I
2
C-bus registers
8.25 EDID memory management
The TDA19977A; TDA19977B embedded EDID memory can be shared with all HDMI
inputs. The embedded EDID memory shares 253 bytes with the three HDMI inputs. In
addition, three bytes are dedicated to the physical address and checksum for each HDMI
input (see Figure 3). This memory is accessible in parallel by all HDMI inputs. You can
share the EDID memory over zero, one, two or three HDMI input(s) as shown in Figure 4.
The content of embedded volatile EDID memory must be programmed using the I
2
C-bus
for each power-on of TDA19977A; TDA19977B. The embedded EDID memory remains
accessible on each HDMI input when the TDA19977A; TDA19977B uses a different
low-power mode.
The “physical address” of each HDMI input can be easily changed with the TDA19977A;
TDA19977B without corrupting the integrity of each DDC-bus.
8.25.1 EDID memory shared over all three HDMI inputs
(1) 253 bytes
+ 3 bytes input A
+ 3 bytes input B
+ 3 bytes input C
+ 1 byte address pointer (subPhys@): this indicates the address in each block where the data for
inputs A, B and C will be copied.
Fig 3. An example of an application with EDID memory shared over all three HDMI
inputs
001aai383
EDID: 253 B
3 B
HDMI
INPUT
I
2
C-bus
CPU
FLASH
(1)
EDID CONTENT
TDA19977
3 B
HDMI
INPUT
3 B
HDMI
INPUT
