®
Technology
SiI 1161
PanelLink Receiver
Data Sheet
Document # SiI-DS-0096-D
SiI 1161 PanelLink Receiver
Data Sheet
SiI-DS-0096-D ii
Silicon Image, Inc.
SiI-DS-0096-D
June 2005
Application Information
To obtain the most updated Application Notes and other useful information for your design, please visit the Silicon
Image web site at www.siimage.com, or contact your local Silicon Image sales office.
Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or
send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.
Trademark Acknowledgment
Silicon Image, the Silicon Image logo, PanelLink
®
and the PanelLink
®
Digital logo are registered trademarks of
Silicon Image, Inc. TMDS
TM
is a trademark of Silicon Image, Inc. VESA
®
is a registered trademark of the Video
Electronics Standards Association. All other trademarks are the property of their respective holders.
Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the
information in this document as necessary. The customer should make sure that they have the most recent data
sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document.
Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.
Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.
All information contained herein is subject to change without notice.
Revision History
Revision Date Comment
-SiI-DS-0096-A
08/2003 Data Sheet
SiI-DS-0096-B
11/2003 Data Sheet Rev B, page 3 - added V
OL
/ I
OL
spec for SDA pin; page 8 –
setup and hold time fixes; page 14 – hold time calculation fixes; page 36
– new signal trace routing example; page 40 – new part number added
SiI-DS-0096-C
1/2004 Part marking spec updated
SiI-DS-0096-D
6/2005 Figure 3, 15, 17, 19, 21, 22, 24, 32 add/update; Ordering Information
update; I
2
C Reset recommendations, T
RESET
timing added;
© 2001, 2002, 2003, 2004, 2005 Silicon Image. Inc.
SiI 1161 PanelLink Receiver
Data Sheet
iii SiI-DS-0096-D
TABLE OF CONTENTS
SiI 1161 Pin Diagram....................................................................................................................1
Functional Description.................................................................................................................2
Electrical Specifications...............................................................................................................3
Absolute Maximum Conditions ................................................................................................................... 3
Normal Operating Conditions ..................................................................................................................... 3
Digital I/O Specifications ............................................................................................................................. 3
General DC Specifications.......................................................................................................................... 4
General AC Specifications .......................................................................................................................... 5
Compatibility Mode Selection Specifications.............................................................................6
SiI 161B (Compatible) Mode DC Specifications ......................................................................................... 6
SiI 161B (Compatible) Mode AC Specifications.......................................................................................... 8
SiI 1161 (Programmable) Mode DC Specifications .................................................................................... 9
SiI 1161 (Programmable) Mode AC Specifications................................................................................... 11
Timing Diagrams.........................................................................................................................15
Pin Descriptions..........................................................................................................................19
Output Pins ............................................................................................................................................... 19
Differential Signal Data Pins ..................................................................................................................... 19
Configuration Pins..................................................................................................................................... 20
Power Management Pins.......................................................................................................................... 20
Power and Ground Pins............................................................................................................................ 21
Feature Information....................................................................................................................22
HSYNC De-jitter Function ......................................................................................................................... 22
Clock Detect Function............................................................................................................................... 22
OCK_INV Function ................................................................................................................................... 22
I
2
C Slave Interface .................................................................................................................................... 23
TFT Panel Data Mapping .......................................................................................................................... 24
Design Recommendations.........................................................................................................31
Differences Between SiI 161B and SiI 1161............................................................................................. 31
Using SiI 1161 in Multiple-Input Applications............................................................................................ 32
Using SiI 1161 to Replace TI TFP401...................................................................................................... 32
Adjusting Equalizer and Bandwidth .......................................................................................................... 33
Voltage Ripple Regulation......................................................................................................................... 34
Decoupling Capacitors.............................................................................................................................. 35
Series Damping Resistors on Outputs...................................................................................................... 36
Receiver Layout ........................................................................................................................................ 37
PCB Ground Planes.................................................................................................................................. 38
Staggered Outputs and Two Pixels per Clock .......................................................................................... 38
Adjusting Output Timings for Loading....................................................................................................... 38
Packaging....................................................................................................................................39
Thermal Design Options ........................................................................................................................... 39
ePad Enhancement .................................................................................................................................. 39
Dimensions and Marking .......................................................................................................................... 41
Ordering Information..................................................................................................................41

SII1161CTU

Mfr. #:
Manufacturer:
Lattice
Description:
UXGA PANELLINK RECEIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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