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SII1161CTU

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
SiI 1161 PanelLink Receiver
Data Sheet
SiI-DS-0096-D 6
Compatibility Mode Selection Specifications
The 1161 design provides new features that were not available on previous TMDS receiver series. To utilize the
new features and ensure backwards compatibility, two mode selections have been defined.
SiI 161B (Compatible) Mode: This mode allows drop-in replacement of SiI 161B and other pin-compatible
receivers, and provides improved performance over other solutions. Strapping MODE (pin 99) = HIGH selects
Compatible Mode.
SiI 1161 (Programmable) Mode. Superior link recovery performance is possible, along with additional output
drive timing margin, when this mode is selected. Strapping MODE (pin 99) = LOW and I2C_MODE# (pin 7) =
LOW selects Programmable Mode.
SiI 161B (Compatible) Mode DC Specifications
The output drive strength is controlled with the ST pin as indicated in Figure 2.
Figure 2. SiI 161B Mode Control of Output Pin Drive Strength
ODCK, DE
ST
ODCK,
DE
Always on settings:
Minimum load = 10pF
ST=1 for load = 20pF
Q[n],HS,VS
ST
Q[n],
HS,VS
Always on settings:
Minimum load = 5pF
ST=1 for load = 10pF
SiI 1161 PanelLink Receiver
Data Sheet
7 SiI-DS-0096-D
The output drive specifications in the Compatible mode are equivalent to the drive on the SiI 161B part.
Table 3. SiI 161B Mode DC Specifications
Strap option: ST=0 (Low Drive Strength)
Parameter Conditions Limits (mA) Notes
ST V
OUT
C
L
Min Typ Max
Data and Controls
I
OHD
Output High Drive 0 2.4V 5pF 3.8 1
I
OLD
Output Low Drive 0 0.8V 5pF 5.5 2
0 0.4V 5pF 3.2 3
ODCK and DE
I
OHC
Output High Drive 0 2.4V 10pF 7.5 4
I
OLC
Output Low Drive 0 0.8V 10pF 11.1
0 0.4V 10pF 6.2
Strap option: ST=1 (High Drive Strength)
Parameter Conditions Limits (mA) Notes
ST V
OUT
C
L
Min Typ Max
Data and Controls
I
OHD
Output High Drive 1 2.4V 10pF 7.4 1
I
OLD
Output Low Drive 1 0.8V 10pF 11.1 2
1 0.4V 10pF 6.3 3
ODCK and DE
I
OHC
Output High Drive 1 2.4V 20pF 14.7 4
I
OLC
Output Low Drive 1 0.8V 20pF 21.2
1 0.4V 20pF 12.3
Notes
1. Output loading is equivalent to one or two CMOS input loads.
2. 0.8V corresponds to LVTTL V
IN
(max).
3. 0.4V corresponds to LVCMOS V
IN
(max).
4. Output loading is equivalent to two or four CMOS input loads.
SiI 1161 PanelLink Receiver
Data Sheet
SiI-DS-0096-D 8
SiI 161B (Compatible) Mode AC Specifications
AC timings are provided here in setup/hold format at 165MHz for ease of direct comparison to the SiI 161B part.
Timing specifications in Table 4 apply to worst-case one pixel per clock mode. For other modes and frequencies
use the SiI 1161 Mode timings and calculation methodology, “Calculating Setup and Hold Times” on Page 12.
Table 4. SiI 161B Mode AC Specifications
Strap option: ST=0 (Low Drive Strength)
Parameter Conditions Limits (ns)
Data, HSYNC, VSYNC Max
D
HLT
1-to-0 Transition C
L
=5pF 2.5
D
LHT
0-to-1 Transition C
L
=5pF 2.0
ODCK, DE Max
D
HLT
1-to-0 Transition C
L
=5pF 1.5
D
LHT
0-to-1 Transition C
L
=5pF 1.7
Timing @ 165MHz Min
OCK_INV=0
Min
OCK_INV=1
T
SETUP
Data C
L
=5pF 0.9 1.2
DE, HSYNC, VSYNC C
L
=5pF 0.2 0.4
T
HOLD
Data C
L
=5pF 2.8 2.4
DE, HSYNC, VSYNC C
L
=5pF 3.6 2.6
Strap option: ST=1 (High Drive Strength)
Parameter Conditions Limits (ns)
Data, HSYNC, VSYNC Max
D
HLT
1-to-0 Transition C
L
=10pF 2.5
D
LHT
0-to-1 Transition C
L
=10pF 2.0
ODCK, DE Max
D
HLT
1-to-0 Transition C
L
=10pF 1.2
D
LHT
0-to-1 Transition C
L
=10pF 1.4
Timing @ 165MHz Min
OCK_INV=0
Min
OCK_INV=1
T
SETUP
Data C
L
=10pF 0.9 1.2
DE, HSYNC, VSYNC C
L
=10pF 0.6 1.1
T
HOLD
Data C
L
=10pF 2.8 2.2
DE, HSYNC, VSYNC C
L
=10pF 3.1 2.1
Notes
1. All transitions are specified at worst case of 70ºC with minimum VCC.
2. ODCK and DE output pins should be loaded with 10pF when ST=0 and 20pF when ST=1. If layout requires only a
point-to-point, one load net, a discrete 10pF capacitor should be added to the net to create these loads. See Figure
3.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

SII1161CTU

Mfr. #:
Buy SII1161CTU
Manufacturer:
Lattice
Description:
UXGA PANELLINK RECEIVER
Lifecycle:
New from this manufacturer.
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