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SII1161CTU

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
SiI 1161 PanelLink Receiver
Data Sheet
27 SiI-DS-0096-D
Table 13. 24-bit One Pixel per Clock Input with 24-bit Two Pixels per Clock Output TFT Mode
TFT VGA Output Tx Input Data Rx Output Data TFT Panel Input
24-bpp 160 164 1161 24-bpp
B0 DIE0 D0 QE0 B0 – 0
B1 DIE1 D1 QE1 B1 – 0
B2 DIE2 D2 QE2 B2 – 0
B3 DIE3 D3 QE3 B3 – 0
B4 DIE4 D4 QE4 B4 – 0
B5 DIE5 D5 QE5 B5 – 0
B6 DIE6 D6 QE6 B6 – 0
B7 DIE7 D7 QE7 B7 – 0
G0 DIE8 D8 QE8 G0 – 0
G1 DIE9 D9 QE9 G1 – 0
G2 DIE10 D10 QE10 G2 – 0
G3 DIE11 D11 QE11 G3 – 0
G4 DIE12 D12 QE12 G4 – 0
G5 DIE13 D13 QE13 G5 – 0
G6 DIE14 D14 QE14 G6 – 0
G7 DIE15 D15 QE15 G7 – 0
R0 DIE16 D16 QE16 R0 – 0
R1 DIE17 D17 QE17 R1 – 0
R2 DIE18 D18 QE18 R2 – 0
R3 DIE19 D19 QE19 R3 – 0
R4 DIE20 D20 QE20 R4 – 0
R5 DIE21 D21 QE21 R5 – 0
R6 DIE22 D22 QE22 R6 – 0
R7 DIE23 D23 QE23 R7 – 0
QO0 B0 – 1
QO1 B1 – 1
QO2 B2 – 1
QO3 B3 – 1
QO4 B4 – 1
QO5 B5 – 1
QO6 B6 – 1
QO7 B7 – 1
QO8 G0 – 1
QO9 G1 – 1
QO10 G2 – 1
QO11 G3 – 1
QO12 G4 – 1
QO13 G5 – 1
QO14 G6 – 1
QO15 G7 – 1
QO16 R0 – 1
QO17 R1 – 1
QO18 R2 – 1
QO19 R3 – 1
QO20 R4 – 1
QO21 R5 – 1
QO22 R6 – 1
QO23 R7 – 1
Shift CLK IDCK IDCK ODCK Shift CLK/2
VSYNC VSYNC VSYNC VSYNC VSYNC
HSYNC HSYNC HSYNC HSYNC HSYNC
DE DE DE DE DE
SiI 1161 PanelLink Receiver
Data Sheet
SiI-DS-0096-D 28
Table 14. 18-bit One Pixel per Clock Input with 18-bit Two Pixels per Clock Output TFT Mode
TFT VGA Output Tx Input Data Tx Output Data TFT Panel Input
18-bpp 160 164 1161 141B 18-bpp
DIE0 D0 QE0
DIE1 D1 QE1
B0 DIE2 D2 QE2 Q0 B0 – 0
B1 DIE3 D3 QE3 Q1 B1 – 0
B2 DIE4 D4 QE4 Q2 B2 – 0
B3 DIE5 D5 QE5 Q3 B3 – 0
B4 DIE6 D6 QE6 Q4 B4 – 0
B5 DIE7 D7 QE7 Q5 B5 – 0
DIE8 D8 QE8
DIE9 D9 QE9
G0 DIE10 D10 QE10 Q6 G0 – 0
G1 DIE11 D11 QE11 Q7 G1 – 0
G2 DIE12 D12 QE12 Q8 G2 – 0
G3 DIE13 D13 QE13 Q9 G3 – 0
G4 DIE14 D14 QE14 Q10 G4 – 0
G5 DIE15 D15 QE15 Q11 G5 – 0
DIE16 D16 QE16
DIE17 D17 QE17
R0 DIE18 D18 QE18 Q12 R0 – 0
R1 DIE19 D19 QE19 Q13 R1 – 0
R2 DIE20 D20 QE20 Q14 R2 – 0
R3 DIE21 D21 QE21 Q15 R3 – 0
R4 DIE22 D22 QE22 Q16 R4 – 0
R5 DIE23 D23 QE23 Q17 R5 – 0
QO0
QO1
QO2 Q18 B0 – 1
QO3 Q19 B1 – 1
QO4 Q20 B2 – 1
QO5 Q21 B3 – 1
QO6 Q22 B4 – 1
QO7 Q23 B5 – 1
QO8
QO9
QO10 Q24 G0 – 1
QO11 Q25 G1 – 1
QO12 Q26 G2 – 1
QO13 Q27 G3 – 1
QO14 Q28 G4 – 1
QO15 Q29 G5 – 1
QO16
QO17
QO18 Q30 R0 – 1
QO19 Q31 R1 – 1
QO20 Q32 R2 – 1
QO21 Q33 R3 – 1
QO22 Q34 R4 – 1
QO23 Q35 R5 – 1
Shift CLK IDCK IDCK ODCK Shift CLK/2 Shift CLK/2
VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC
HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC
DE DE DE DE DE DE
SiI 1161 PanelLink Receiver
Data Sheet
29 SiI-DS-0096-D
Table 15. Two Pixels per Clock Input with One Pixel per Clock Output TFT Mode
TFT VGA Output Tx Input Data Rx Output Data TFT Panel Input
24-bpp 18-bpp 160 1161 141B 24-bpp 18-bpp
B0 – 0 DIE0 QE0 Q0 B0
B1 – 0 DIE1 QE1 Q1 B1
B2 – 0 B0 – 0 DIE2 QE2 Q2 B2 B0
B3 – 0 B1 – 0 DIE3 QE3 Q3 B3 B1
B4 – 0 B2 – 0 DIE4 QE4 Q4 B4 B2
B5 – 0 B3 – 0 DIE5 QE5 Q5 B5 B3
B6 – 0 B4 – 0 DIE6 QE6 Q6 B6 B4
B7 – 0 B5 – 0 DIE7 QE7 Q7 B7 B5
G0 – 0 DIE8 QE8 Q8 G0
G1 – 0 DIE9 QE9 Q9 G1
G2 – 0 G0 – 0 DIE10 QE10 Q10 G2 G0
G3 – 0 G1 – 0 DIE11 QE11 Q11 G3 G1
G4 – 0 G2 – 0 DIE12 QE12 Q12 G4 G2
G5 – 0 G3 – 0 DIE13 QE13 Q13 G5 G3
G6 – 0 G4 – 0 DIE14 QE14 Q14 G6 G4
G7 – 0 G5 – 0 DIE15 QE15 Q15 G7 G5
R0 – 0 DIE16 QE16 Q16 R0
R1 – 0 DIE17 QE17 Q17 R1
R2 – 0 R0 – 0 DIE18 QE18 Q18 R2 R0
R3 – 0 R1 – 0 DIE19 QE19 Q19 R3 R1
R4 – 0 R2 – 0 DIE20 QE20 Q20 R4 R2
R5 – 0 R3 – 0 DIE21 QE21 Q21 R5 R3
R6 – 0 R4 – 0 DIE22 QE22 Q22 R6 R4
R7 – 0 R5 – 0 DIE23 QE23 Q23 R7 R5
B0 – 1 DIO0
B1 – 1 DIO1
B2 – 1 B0 – 1 DIO2
B3 – 1 B1 – 1 DIO3
B4 – 1 B2 – 1 DIO4
B5 – 1 B3 – 1 DIO5
B6 – 1 B4 – 1 DIO6
B7 – 1 B5 – 1 DIO7
G0 – 1 DIO8
G1 – 1 DIO9
G2 – 1 G0 – 1 DIO10
G3 – 1 G1 – 1 DIO11
G4 – 1 G2 – 1 DIO12
G5 – 1 G3 – 1 DIO13
G6 – 1 G4 – 1 DIO14
G7 – 1 G5 – 1 DIO15
R0 – 1 DIO16
R1 – 1 DIO17
R2 – 1 R0 – 1 DIO18
R3 – 1 R1 – 1 DIO19
R4 – 1 R2 – 1 DIO20
R5 – 1 R3 – 1 DIO21
R6 – 1 R4 – 1 DIO22
R7 – 1 R5 – 1 DIO23
ShiftClk/2 ShiftClk/2 IDCK ODCK ODCK ShiftClk ShiftClk
VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC
HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC
DE DE DE DE DE DE DE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

SII1161CTU

Mfr. #:
Buy SII1161CTU
Manufacturer:
Lattice
Description:
UXGA PANELLINK RECEIVER
Lifecycle:
New from this manufacturer.
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