SiI 1161 PanelLink Receiver
Data Sheet
13 SiI-DS-0096-D
Table 7 shows the calculations required for determining setup and hold timings using the clock period T
ODCK
specific to the clock frequency, also bringing in the clock duty cycle as required when OCK_INV=0. The setup
and hold times apply to DE, VSYNC, HSYNC and Data output pins, as long as the appropriate T
CK2OUT
value is
used for the calculation in each case. The table also shows calculated setup and hold times for commonly used
ODCK frequencies.
Table 7. Sample Calculation of Data Output Setup and Hold Times – OCK_INV=0
Symbol Parameter
Frequency
T
ODCK
T
CK2OUT
(data) Result
Data Setu
Time to ODCK
25 MHz 40 ns Max =40*40% - 1.5 = 14.5ns
=T
ODCK
*T
DUTY
{min) 82.5 MHz 12 ns =1.5 =12*40% - 1.5 = 3.3ns
T
SU
-T
CK2OUT
{max} 165 MHz 6 ns =6*40% - 1.5 = 0.9ns
Data Hold Time from ODCK
25 MHz 40 ns Min =40*40% + 0.4 = 16.4ns
=T
ODCK
* (1 - T
DUTY
{max}) 82.5 MHz 12 ns =0.4 =12*40% + 0.4 = 5.2ns
T
HD
+ T
CK2OUT
{min} 165 MHz 6 ns =6*40% + 0.4 = 2.8ns
OCK_INV=1 Case
For OCK_INV=1, the timing is similar to that previously discussed. The worst-case setup time occurs when the
clock to output delay is at a maximum (latest data) and the ODCK duty cycle is at a minimum (earliest falling
edge). Conversely, the worst case hold time occurs when the clock to output delay is at a minimum (earliest next
data) and the ODCK duty cycle is at a maximum (latest falling edge). This timing relationship is shown in Figure
6. The rising active ODCK edge is shown with an arrowhead.
Figure 6. Receiver Output Setup and Hold Times – OCK_INV=1
Note: For Staggered Output timing in 2Pix/clk mode, refer to Figure 15.
T
DUTY
= min
T
CK2OUT
= max
External clock
ODCK
with
OCK_INV=1
Q
DE
VSYNC
HSYNC
50%
T
HD
T
SU
T
CK2OUT
= min
T
DUTY
= max
50%
Edge used
internally to clock
out Data (Q), DE,
VSYNC, HSYNC
External logic uses
this rising clock edge
to sample data
Internal
Clock
T
DLY
- inverter delays
