SiI 1161 PanelLink Receiver
Data Sheet
11 SiI-DS-0096-D
SiI 1161 (Programmable) Mode AC Specifications
SiI 1161 Mode AC timings are based on “Clock to Output” (CK2OUT) timing measurements. This methodology
provides a precise means of calculating setup and hold at any frequency and in any chip operating mode. C
L
indicates the load on the ODCK line. The load on the data/control line involved depends on CKST: for CKST=1,
the control/data pin load is C
L
; for CKST=0, the load is 2x C
L
.
Table 6. SiI 1161 Mode AC Specifications
Program Option: ST=0 (Low Drive Strength)
Parameter Conditions Limits (ns)
Data, HSYNC, VSYNC CKST ST C
L
Max
D
HLT
1-to-0 Transition X 0 5pF 2.5
D
LHT
0-to-1 Transition X 0 5pF 2.0
ODCK, DE CKST ST C
L
Max
D
HLT
1-to-0 Transition 1 0 5pF 1X clock drive 2.5
0 0 10pF 2X clock drive 1.5
D
LHT
0-to-1 Transition 1 0 5pF 1X clock drive 2.7
0 0 10pF 2X clock drive 1.7
Clock-to-Output Timing CKST ST C
L
Min Max
OCK_INV Setting 0 1 0 1
T
CK2OUT
1 0 5pF 0.4 0.0 1.5 1.2
ODCK to Data
0 0 10pF 0.4 -0.1 1.5 1.0
T
CK2OUT
1 0 5pF 1.2 0.2 2.2 2.0
ODCK to DE,
HSYNC,
VSYNC
0 0 10pF 0.8 0.1 2.2 1.7
Program Option: ST=1 (High Drive Strength)
Parameter Conditions Limits (ns)
Data, HSYNC, VSYNC CKST ST C
L
Max
D
HLT
1-to-0 Transition X 1 10pF 2.5
D
LHT
0-to-1 Transition X 1 10pF 2.0
ODCK, DE CKST ST C
L
Max
D
HLT
1-to-0 Transition 1 1 10pF 2X clock drive 1.9
0 1 20pF 4X clock drive 1.2
D
LHT
0-to-1 Transition 1 1 10pF 2X clock drive 1.7
0 1 20pF 4X clock drive 1.4
Clock-to-Output Timing CKST ST C
L
Min Max
OCK_INV Setting 0 1 0 1
T
CK2OUT
1 1 10pF 0.4 -0.2 1.5 1.2
ODCK to Data
0 1 20pF 0.0 -0.8 1.4 1.0
T
CK2OUT
1 1 10pF 0.7 -0.3 1.8 1.3
ODCK to DE,
HSYNC,
VSYNC
0 1 20pF 0.1 -0.3 1.9 1.0
Notes
1. Output loading is equivalent to one (5pF), two (10pF) or four (20pF) CMOS input loads.
2. All transition time specifications at 70°C, minimum VCC.
3. Timing specifications in Table 6 apply to both one pixel per clock and two pixel per clock modes.
