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SII1161CTU

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
SiI 1161 PanelLink Receiver
Data Sheet
15 SiI-DS-0096-D
Timing Diagrams
10pF / 5pF
SiI
1161
D
HLT
2.0 V 2.0 V
0.8 V
0.8
D
LHT
Figure 7. Digital Output Transition Times
R
CIH
R
CIL
2.0 V
0.8 V
0.8 V
2.0 V
Figure 8. Receiver Clock Cycle/High/Low Times
RX0
RX1
RX2
T
CCS
V
DIFF=0V
V
DIFF=0V
Figure 9. Channel-to-Channel Skew Timing
SiI 1161 PanelLink Receiver
Data Sheet
SiI-DS-0096-D 16
RXC+
QE[23:0], QO[23:0],
DE, CTL[3:1]
VSYNC, HSYNC
T
CLKPD
..
.
..
.
Figure 10. Receiver Clock-to-Output Delay and Duty Cycle Limits
Figure 11. Output Signals Disabled Timing from Clock Inactive
Figure 12. Wake-Up on Clock Detect
RXC+
SCDT
T
CLKPU
+ T
FSC
T
DUTY
= min
T
CK2OUT
= max
ODCK
(OCK_INV=0)
Q
DE
VSYNC
HSYNC
50%
T
HD
T
SU
T
CK2OUT
= min
T
DUTY
= max
50%
R
CIP
SiI 1161 PanelLink Receiver
Data Sheet
17 SiI-DS-0096-D
T
PDL
QE[23:0], QO[23:0],
DE, CTL[3:1],
VSYNC, HSYNC
PD#
V
IL
Figure 13. Output Signals Disabled Timing from PD# Active
Figure 14. SCDT Timing from DE Inactive or Active
ODCK
DE
QE[23:0]
QO[23:0]
FIRST EVEN DATA SECOND EVEN DATA
Internal
ODCK * 2
FIRST ODD DATA SECOND ODD DATA
T
ST
Figure 15. Two Pixels per Clock Staggered Output Timing Diagram
DE
SCDT
DE
SCDT
T
HSC
T
FSC
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

SII1161CTU

Mfr. #:
Buy SII1161CTU
Manufacturer:
Lattice
Description:
UXGA PANELLINK RECEIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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