AD7859ASZ Datasheet AD7859ASZ, AD7859APZ, AD7859BSZ | P19-P21

AD7859/AD7859L

REV. A

–18–

PSRR – dB

INPUT FREQUENCY – kHz

–78

–80

–88

0 10020 40 60 80

–82

–84

–86

= DV

= 3.3V/5.0V

100mV pk-pk SINEWAVE ON AV

–90

3.3V

5.0V

Figure 20. PSRR vs. Frequency

POWER-DOWN OPTIONS

The AD7859/AD7859L provides flexible power management to

allow the user to achieve the best power performance for a given

throughput rate. The power management options are selected

by programming the power management bits, PMGT1 and

PMGT0, in the control register and by use of the

SLEEP pin.

Table VII summarizes the power-down options that are avail-

able and how they can be selected by using either software,

hardware or a combination of both. The AD7859/AD7859L can

be fully or partially powered down. When fully powered down,

all the on-chip circuitry is powered down and I

is 10 µA typ.

If a partial power-down is selected, then all the on-chip circuitry

except the reference is powered down and I

is 400 µA typ.

The choice of full or partial power-down does not give any sig-

nificant improvement in throughput with a power-down between

conversions. This is discussed in the next section—Power-Up

Times. But a partial power-down does allow the on-chip refer-

ence to be used externally even though the rest of the AD7859/

AD7859L circuitry is powered down. It also allows the

AD7859/AD7859L to be powered up faster after a long power-

down period when using the on-chip reference (See Power-Up

Times—Using On-Chip Reference).

When using the

SLEEP pin, the power management bits

PMGT1 and PMGT0 should be set to zero. Bringing the

SLEEP pin logic high ensures normal operation, and the part

does not power down at any stage. This may be necessary if the

part is being used at high throughput rates when it is not pos-

sible to power down between conversions. If the user wishes to

power down between conversions at lower throughput rates

(i.e., <100 kSPS for the AD7859 and <60 kSPS for the

AD7859L) to achieve better power performances, then the

SLEEP pin should be tied logic low.

If the power-down options are to be selected in software only,

then the

SLEEP pin should be tied logic high. By setting the

power management bits PMGT1 and PMGT0 as shown in

Table VII, a Full Power-Down, Full Power-Up, Full Power-

Down Between Conversions, and a Partial Power-Down Be-

tween Conversions can be selected.

A combination of hardware and software selection can also be

used to achieve the desired effect.

Table VII. Power Management Options

PMGT1 PMGT0 SLEEP

Bit Bit Pin Comment

0 0 0 Full Power-Down Between

Conversions (HW / SW)

0 0 1 Full Power-Up (HW / SW)

0 1 X Full Power-Down Between

Conversions (SW )

1 0 X Full Power-Down (SW)

1 1 X Partial Power-Down Between

Conversions (SW)

NOTE

SW = Software selection, HW = Hardware selection.

POWER-UP TIMES

Using An External Reference

When the AD7859/AD7859L are powered up, the parts are

powered up from one of two conditions. First, when the power

supplies are initially powered up and, secondly, when the parts

are powered up from either a hardware or software power-down

(see last section).

When AV

and DV

are powered up, the AD7859/AD7859L

enters a mode whereby the CONVST signal initiates a timeout

followed by a self-calibration. The total time taken for this time-

out and calibration is approximately 70 ms—see Calibration on

Power-Up in the calibration section of this data sheet. During

power-up the functionality of the

SLEEP pin is disabled, i.e.,

the part will not power down until the end of the calibration if

SLEEP is tied logic low. The power-up calibration mode can be

disabled if the user writes to the control register before a

CONVST signal is applied. If the time out and self-calibration

are disabled, then the user must take into account the time

required by the AD7859/AD7859L to power up before a self-

calibration is carried out. This power-up time is the time taken

for the AD7859/AD7859L to power up when power is first

applied (300 µs typ) or the time it takes the external reference to

settle to the 12-bit level—whichever is the longer.

The AD7859/AD7859L powers up from a full hardware or soft-

ware power-down in 5 µs typ. This limits the throughput which

the part is capable of to 100 kSPS for the AD7859 and 60 kSPS

for the AD7859L when powering down between conversions.

Figure 21 shows how power-down between conversions is

implemented using the

CONVST pin. The user first selects the

power-down between conversions option by using the

SLEEP

pin and the power management bits, PMGT1 and PMGT0, in

the control register. See last section. In this mode the AD7859/

AD7859L automatically enters a full power-down at the end of

a conversion, i.e., when BUSY goes low. The falling edge of the

CONVST pulse causes the part to power up. Assuming the

external reference is left powered up, the AD7859/AD7859L

should be ready for normal operation 5 µs after this falling edge.

The rising edge of

CONVST initiates a conversion so the

CONVST pulse should be at least 5 µs wide. The part automati-

cally powers down on completion of the conversion. Where the

software convert start is used, the part may be powered up in

software before a conversion is initiated.

AD7859/AD7859L

REV. A

–19–

POWER VS. THROUGHPUT RATE

The main advantage of a full power-down after a conversion is

that it significantly reduces the power consumption of the part

at lower throughput rates. When using this mode of operation,

the AD7859/AD7859L is only powered up for the duration of

the conversion. If the power-up time of the AD7859/AD7859L

is taken to be 5 µs and it is assumed that the current during

power up is 4.5 mA/1.5 mA typ, then power consumption as a

function of throughput can easily be calculated. The AD7859

has a conversion time of 4.6 µs with a 4 MHz external clock and

the AD7859L has a conversion time of 9 µs with a 1.8 MHz

clock. This means the AD7859/AD7859L consumes 4.5 mA/

1.5 mA typ for 9.6 µs/14 µs in every conversion cycle if the parts

are powered down at the end of a conversion. The two graphs,

Figure 24 and Figure 25, show the power consumption of the

AD7859 and AD7859L for V

= 3 V as a function of through-

put. Table VIII lists the power consumption for various

throughput rates.

Table VIII. Power Consumption vs. Throughput

Power Power

Throughput Rate AD7859 AD7859L

1 kSPS 130 µW65µW

10 kSPS 1.3 mW 650 µW

20 kSPS 2.6 mW 1.25 mW

50 kSPS 6.48 mW 3.2 mW

1.8MHz

OSCILLATOR

AIN(+)

AIN(–)

REF1

REF2

SLEEP

DB15

DB0

CONVST

AGND

DGND

CLKIN

REF

/REF

OUT

AD7859L

ANALOG

SUPPLY

+3V

0.1µF

10µF

0.1µF

0.01µF

CONVERSION

START SIGNAL

0.1µF

CAL

0V TO 2.5V

INPUT

OPTIONAL

EXTERNAL

REFERENCE

W/B

BUSY

REF192

CURRENT,

I = 1.5mA TYP

LOW

POWER

µC/µP

Figure 23. Typical Low Power Circuit

CONVST

BUSY

5µs

4.6µs

CONVERT

START CONVERSION ON RISING EDGE

POWER UP ON FALLING EDGE

POWER-UP

TIME

NORMAL

OPERATION

FULL

POWER-DOWN

POWER-UP

TIME

Figure 21. Using the CONVST Pin to Power Up the AD7859

for a Conversion

Using The Internal (On-Chip) Reference

As in the case of an external reference, the AD7859/AD7859L

can power up from one of two conditions, power-up after the

supplies are connected or power-up from hardware/software

power-down.

When using the on-chip reference and powering up when AV

and DV

are first connected, it is recommended that the

power-up calibration mode be disabled as explained above.

When using the on-chip reference, the power-up time is effec-

tively the time it takes to charge up the external capacitor on the

REF

/REF

OUT

pin. This time is given by the equation:

= 9 × R × C

where R ≈ 150K and C = external capacitor.

The recommended value of the external capacitor is 100 nF;

this gives a power-up time of approximately 135 ms before a

calibration is initiated and normal operation should commence.

When C

REF

is fully charged, the power-up time from a hardware

or software power-down reduces to 5 µs. This is because an in-

ternal switch opens to provide a high impedance discharge path

for the reference capacitor during power-down—see Figure 22.

An added advantage of the low charge leakage from the refer-

ence capacitor during power-down is that even though the refer-

ence is being powered down between conversions, the reference

capacitor holds the reference voltage to within 0.5 LSBs with

throughput rates of 100 samples/second and over with a full

power-down between conversions. A high input impedance op

amp like the AD707 should be used to buffer this reference

capacitor if it is being used externally. Note, if the AD7859/

AD7859L is left in its powered-down state for more than

100 ms, the charge on C

REF

will start to leak away and the

power-up time will increase. If this long power-up time is a

problem, the user can use a partial power-down for the last con-

version so the reference remains powered up.

BUF

ON-CHIP

REFERENCE

TO OTHER

CIRCUITRY

SWITCH OPENS

DURING POWER-DOWN

REF

IN/OUT

EXTERNAL

CAPACITOR

Figure 22. On-Chip Reference During Power-Down

AD7859/AD7859L

REV. A

–20–

POWER – mW

THROUGHPUT RATE – kSPS

0.1

0.01

0102468

AD7859 FULL POWER-DOWN

= 3V CLKIN = 4MHz

ON-CHIP REFERENCE

Figure 24. Power vs. Throughput AD7859

POWER – mW

THROUGHPUT RATE – kSPS

0.1

0.01

0204 8 12 16

AD7859L FULL POWER-DOWN

= 3V CLKIN = 1.8MHz

ON-CHIP REFERENCE

Figure 25. Power vs. Throughput AD7859L

POWER – mW

THROUGHPUT RATE – kSPS

0.01

05010 20 30 40

0.1

AD7859 FULL POWER-DOWN

= 3V CLKIN = 4MHz

ON-CHIP REFERENCE

Figure 26. Power vs. Throughput AD7859

POWER – mW

THROUGHPUT RATE – kSPS

0.01

05010 20 30 40

0.1

AD7859L FULL POWER-DOWN

= 3V CLKIN = 1.8MHz

ON-CHIP REFERENCE

Figure 27. Power vs. Throughput AD7859L

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

AD7859ASZ

Mfr. #:

Buy AD7859ASZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 8-Ch 12-Bit

Lifecycle:

New from this manufacturer.

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AD7859ASZ

AD7859ASZ

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