REV. A
–3–
Parameter A Version
1
B Version
1
Units Test Conditions/Comments
CONVERSION RATE t
CLKIN
× 18
Conversion Time 4.5 (10) 4.5 µs max (L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN)
Track/Hold Acquisition Time 0.5 (1) 0.5 µs min (L Versions Only, –40°C to +85°C, 1.8 MHz CLKIN)
POWER REQUIREMENTS
AV
DD,
DV
DD
+3.0/+5.5 +3.0/+5.5 V min/max
I
DD
Normal Mode
5
5.5 (1.95) 5.5 mA max AV
DD
= DV
DD
= 4.5 V to 5.5 V. Typically 4.5 mA
5.5 (1.95) 5.5 mA max AV
DD
= DV
DD
= 3.0 V to 3.6 V. Typically 4.0 mA
Sleep Mode
6
With External Clock On 10 10 µA typ Full Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 0.
400 400 µA typ Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1.
With External Clock Off 5 5 µA max Typically 1 µA. Full Power-Down. Power Management
Bits in Control Register Set as PMGT1 = 1, PMGT0 = 0.
200 200 µA typ Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1.
Normal Mode Power Dissipation 30 (10) 30 (10) mW max V
DD
= 5.5 V: Typically 25 mW (8); SLEEP = V
DD
20 (6.5) 20 (6.5) mW max V
DD
= 3.6 V: Typically 15 mW (5.4); SLEEP = V
DD
Sleep Mode Power Dissipation
With External Clock On 55 55 µW typ V
DD
= 5.5 V; SLEEP = 0 V
36 36 µW typ V
DD
= 3.6 V; SLEEP = 0 V
With External Clock Off 27.5 27.5 µW max V
DD
= 5.5 V: Typically 5.5 µW; SLEEP = 0 V
18 18 µW max V
DD
= 3.6 V: Typically 3.6 µW; SLEEP = 0 V
SYSTEM CALIBRATION
Offset Calibration Span
7
+0.05 × V
REF
/–0.05 × V
REF
V max/min Allowable Offset Voltage Span for Calibration
Gain Calibration Span
7
+1.025 × V
REF
/–0.975 × V
REF
V max/min Allowable Full-Scale Voltage Span for Calibration
NOTES
1
Temperature range as follows: A, B Versions, –40°C to +85°C.
2
Specifications apply after calibration.
3
SNR calculation includes distortion and noise components.
4
Not production tested, guaranteed by characterization at initial product release.
5
All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV
DD
. No load on the digital outputs. Analog inputs @ AGND.
6
CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV
DD
. No load on the digital outputs.
Analog inputs @ AGND.
7
The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7859/AD7859L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ±0.05 × V
REF
,
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
REF
± 0.025 × V
REF
).
This is explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
AD7859/AD7859L
