AD7859/AD7859L
REV. A
–6–
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7859/AD7859L, it is
defined as:
THD (dB) = 20log
(V
2
2
+V
3
2
+V
4
2
+V
5
2
+V
6
2
)
V
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in fre-
quency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Unipolar Offset Error
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)
when operating in the unipolar mode.
Positive Full-Scale Error
This applies to the unipolar and bipolar modes and is the devia-
tion of the last code transition from the ideal AIN(+) voltage
(AIN(–) + Full Scale – 1.5 LSB) after the offset error has been
adjusted out.
Negative Full-Scale Error
This applies to the bipolar mode only and is the deviation of the
first code transition (10 . . . 000 to 10 . . . 001) from the ideal
AIN(+) voltage (AIN(–) – V
REF
/2 + 0.5 LSB).
Bipolar Zero Error
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode and the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ±1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental sig-
nals up to half the sampling frequency (f
S
/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N +1.76)dB
Thus for a 12-bit converter, this is 74 dB.
AD7859/AD7859L
REV. A
–7–
PIN FUNCTION DESCRIPTION
Mnemonic Description
CONVST Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold
mode and starts conversion. When this input is not used, it should be tied to DV
DD
.
RD Read Input. Active low logic input. Used in conjunction with CS to read from internal registers.
WR Write Input. Active low logic input. Used in conjunction with CS to write to internal registers.
CS Chip Select Input. Active low logic input. The device is selected when this input is active.
REF
IN
/ Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
REF
OUT
reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears at the
pin. This pin can be overdriven by an external reference or can be taken as high as AV
DD
. When this pin is tied to
AV
DD
, then the C
REF1
pin should also be tied to AV
DD
.
AV
DD
Analog Supply Voltage, +3.0 V to +5.5 V.
AGND Analog Ground. Ground reference for track/hold, reference and DAC.
DV
DD
Digital Supply Voltage, +3.0 V to +5.5 V.
DGND Digital Ground. Ground reference point for digital circuitry.
C
REF1
Reference Capacitor (0.1 µF multilayer ceramic). This external capacitor is used as a charge source for the inter-
nal DAC. The capacitor should be tied between the pin and AGND.
C
REF2
Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip refer-
ence. The capacitor should be tied between the pin and AGND.
AIN1–AIN8 Analog Inputs. Eight analog inputs which can be used as eight single ended inputs (referenced to AGND) or four
pseudo differential inputs. Channel configuration is selected by writing to the control register. None of the inputs
can go below AGND or above AV
DD
at any time. See Table III for channel selection.
W/
B Word/Byte input. When this input is at a logic 1, data is transferred to and from the AD7859/AD7859L in 16-bit
words on pins DB0 to DB15. When this pin is at a Logic 0, byte transfer mode is enabled. Data is transferred on
pins DB0 to DB7 and pin DB8/HBEN assumes its HBEN functionality.
DB0–DB7 Data Bits 0 to 7. Three state data I/O pins that are controlled by
CS, RD and WR. Data output is straight binary
(unipolar mode) or twos complement (bipolar mode).
DB8/HBEN Data Bit 8/High Byte Enable. When W/
B is high, this pin acts as Data Bit 7, a three state data I/O pin that is con-
trolled by
CS, RD and WR. When W/B is low, this pin acts as the High Byte Enable pin. When HBEN is low,
then the low byte of data being written to or read from the AD7859/AD7859L is on DB0 to DB7. When HBEN
is high, then the high byte of data being written to or read from the AD7859/AD7859L is on DB0 to DB7.
DB9–DB15 Data Bits 9 to 15. Three state data I/O pins that are controlled by
CS, RD and WR. Data output is straight bi-
nary (unipolar mode) or twos complement (bipolar mode).
CLKIN Master Clock Signal for the device (4 MHz for AD7859, 1.8 MHz for AD7859L). Sets the conversion and calibra-
tion times.
CAL Calibration Input. A logic 0 in this pin resets all logic. A rising edge on this pin initiates a calibration. This input
overrides all other internal operations.
BUSY Busy Output. The busy output is triggered high when a conversion or a calibration is initiated, and remains high
until the conversion or calibration is completed.
SLEEP Sleep Input. This pin is used in conjunction with the PGMT0 and PGMT1 bits in the control register to deter-
mine the power-down mode. Please see the “Power-Down Options” section for details.
NC No connect pins. These pins should be left unconnected.
AD7859/AD7859L
REV. A
–8–
AD7859/AD7859L ON-CHIP REGISTERS
The AD7859/AD7859L powers up with a set of default conditions. The only writing that is required is to select the channel configu-
ration. Without performing any other write operations, the AD7859/AD7859L still retains the flexibility for performing a full power-
down and a full self-calibration.
Extra features and flexibility such as performing different power-down options, different types of calibrations, including system cali-
bration, and software conversion start can be selected by writing to the part.
The AD7859/AD7859L contains a Control register, ADC output data register, Status register, Test register and 10 Cali-
bration registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test
and calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
When writing to the AD7859/AD7859L, a 16-bit word of data must be transferred. The 16 bits of data is written as either a 16-bit
word, or as two 8-bit bytes, depending on the logic level at the W/
B pin. When W/B is high, the 16 bits are transferred on DB0 to
DB15, where DB0 is the LSB and DB15 is the MSB of the write. When W/
B is low, DB8/HBEN assumes its HBEN functionality
and data is transferred in two 8-bit bytes on pins DB0 to DB7, pin DB0 being the LSB of each transfer and pin DB7 being the MSB.
When writing to the AD7859/AD7859L in byte mode, the low byte must be written first followed by the high byte. The two MSBs
of the complete 16-bit word, ADDR1 and ADDR0, are decoded to determine which register is addressed, and the 14 LSBs are writ-
ten to the addressed register. Table I shows the decoding of the address bits, while Figure 2 shows the overall write register hierarchy.
Table I. Write Register Addressing
ADDR1 ADDR0 Comment
0 0 This combination does not address any register.
0 1 This combination addresses the TEST REGISTER. The 14 LSBs of data are written to the test register.
1 0 This combination addresses the CALIBRATION REGISTERS. The 14 LSBs of data are written to the
selected calibration register.
1 1 This combination addresses the CONTROL REGISTER. The 14 LSBs of data are written to the control
register.
Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 3 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register. As with writing to the AD7859/AD7859L either word or byte mode can be used. When reading
from the calibration registers in byte mode, the low byte must be read first.
Once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register un-
til the read selection bits are changed in the control register.
Table II. Read Register Addressing
RDSLT1 RDSLT0 Comment
0 0 All successive read operations are from the ADC OUTPUT DATA REGISTER. This is the default power-
up setting. There is always four leading zeros when reading from the ADC output data register.
0 1 All successive read operations are from the TEST REGISTER.
1 0 All successive read operations are from the CALIBRATION REGISTERS.
1 1 All successive read operations are from the STATUS REGISTER.
TEST
REGISTER
CALIBRATION
REGISTERS
STATUS
REGISTER
GAIN (1)
OFFSET (1)
DAC (8)
GAIN (1)
OFFSET (1)
OFFSET (1) GAIN (1)
01 10 11
00 01 10 11
CALSLT1, CALSLT0
DECODE
ADC OUTPUT
DATA REGISTER
00
RDSLT1, RDSLT0
DECODE
Figure 3. Read Register Hierarchy/Address Decoding
ADDR1, ADDR0
DECODE
TEST
REGISTER
CONTROL
REGISTER
GAIN (1)
OFFSET (1)
DAC (8)
GAIN (1)
OFFSET (1)
OFFSET (1) GAIN (1)
01 10 11
00 01 10 11
CALSLT1, CALSLT0
DECODE
CALIBRATION
REGISTERS
Figure 2. Write Register Hierarchy/Address Decoding

AD7859ASZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 8-Ch 12-Bit
Lifecycle:
New from this manufacturer.
Delivery:
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