OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD7859ASZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
AD7859/AD7859L
REV. A
–24–
DATA
VALID
DATA
VALID
t
16
t
15
t
17
t
14
t
13
t
CONVERT
t
1
t
18
t
5
t
6
t
7
t
8
t
9
*W/B PIN LOGIC HIGH
BUSY
CS
WR
DB0 – DB15
CONVST
RD
INTERNAL
DATA
LATCH
OLD DATA NEW DATA
Figure 35. Read and Write Cycle Timing Diagram for 16-Bit Transfers
Figure 35 shows the read cycle timing diagram for 16-bit trans-
fers for the AD7859. When operated in word mode, the HBEN
input does not exist, and only the first read operation is required
to access data from the AD7859. Valid data, in this case, is pro-
vided on DB0–DB15. When operated in byte mode, the two
read cycles shown in Figure 36 are required to access the full data
word from the AD7859. Note that in byte mode, the order of
successive read operations is important when reading the cali-
bration registers. This is because the register file address pointer
is incremented on a high byte read as explained in the calibra-
tion register section of this data sheet. In this case the order of
the read should always be Low Byte–High Byte. In Figure 36,
the first read places the lower 8 bits of the full data word on
DB0–DB7 and the second read places the upper 8 bits of the
data word on DB0–DB7.
The
CS and RD signals are gated internally and level-triggered
active low. In either word or byte mode,
CS and RD may be
tied together as the timing specification for t
5
and t
6
is 0 ns min.
The data is output a time t
8
after both CS and RD go low. The
RD rising should be used to latch data by the user and after a
time t
9
the data lines will become three-stated.
PARALLEL INTERFACE
The AD7859 provides a flexible, high speed, parallel interface.
This interface is capable of operating in either word (with the
W/
B pin tied high) or byte (with W/B tied low) mode. A detailed
description of the different interface arrangements follows.
Reading
With the W/B pin at a logic high, the AD7859 interface operates
in word mode. In this case, a single read operation from the
device accesses the word on pins DB0 to DB15 (for a data read,
the 12-bit conversion result appears on DB0–DB11). DB0 is
the LSB of the word. The DB8/HBEN pin assumes its DB8
function. With the W/
B pin at a logic low, the AD7859 interface
operates in byte mode. In this case, the DB8/HBEN pin as-
sumes its HBEN function. Data to be accessed from the
AD7859 must be accessed in two read operations with 8 bits of
data provided by the AD7859 on DB0–DB7 for each of the
read operations. The HBEN pin determines whether the read
operation accesses the high byte or low byte of the 16-bit word.
For a low byte read, DB0 provides the LSB of the 16-bit word.
For a high byte read DB0 provides data bit 8 of the 16-bit word
with DB7 providing the MSB of the 16-bit word.
t
3
t
4
t
3
t
4
t
5
t
10
t
6
t
7
t
8
t
9
LOW BYTE HIGH BYTE
*
W/B PIN LOGIC LOW
HBEN
CS
RD
DB0 – DB7
Figure 36. Read Cycle Timing for Byte Mode Operation
AD7859/AD7859L
REV. A
–25–
t
11
t
12
t
11
t
12
t
13
t
14
t
15
t
16
t
17
LOW BYTE HIGH BYTE
*W/B PIN LOGIC LOW
HBEN
CS
WR
DB0 – DB7
Figure 37. Write Cycle Timing for Byte Mode Operation
Writing
With W/B at a logic high, a single write operation transfers the
full data word to the AD7859. The DB8/HBEN pin assumes its
DB8 function. Data to be written to the AD7859 should be pro-
vided on the DB0–DB15 inputs with DB0 the LSB of the data
word. With W/
B at a logic low, the AD7859 requires two write
operations to transfer a full 16-bit word. DB8/HBEN assumes
its HBEN function. Data to be written to the AD7859 should
be provided on the DB0–DB7 inputs. HBEN determines
whether the byte which is to be written is high byte or low byte
data. The low byte of the data word should be written first with
DB0 the LSB of the full data word. For the high byte write,
HBEN should be high and the data on the DB0 input should be
data bit 8 of the 16-bit word with the data on DB7 the MSB of
the 16-bit word.
Figure 35 shows the write cycle timing diagram for the AD7859.
When operated in word mode, the HBEN input does not exist
and only the first write operation is required to write data to the
AD7859. Data should be provided on DB0–DB15. When oper-
ated in byte mode, the two write cycles shown in Figure 37 are
required to write the full data word to the AD7859. In Figure 37,
the first write transfers the lower 8 bits of the full data from
DB0–DB7 and the second write transfers the upper 8 bits of the
data word from DB0-DB7.
The
CS and WR signals are gated internally. CS and WR may
be tied together as the timing specification for t
13
and t
14
is 0 ns
min. The data is latched on the rising edge of
WR. The data
needs to be set up a time t
16
before the WR rising edge and held
for a time t
17
after the WR rising edge.
Resetting the Parallel Interface
In the case where incorrect data is inadvertently written to the
AD7859, there is a possibility that the Test Register contents
may have been altered. If there is a suspicion that this may have
happened and the part is not operating as expected, a 16-bit
word 0000 0000 0000 0010 should be written to the AD7859 to
restore the Test Register contents to the default value.
MICROPROCESSOR INTERFACING
Interfacing the AD7859/AD7859L to a 16-Bit Data Bus
The parallel port on the AD7859 allows the device to be inter-
faced to microprocessors or DSP processors as a memory-
mapped or I/O-mapped device. The
CS and RD inputs are
common to all memory peripheral interfacing. Typical inter-
faces to different processors are shown in Figures 38 to 42. In
all the interfaces shown, an external timer controls the
CONVST
input of the AD7859/AD7859L, the BUSY output interrupts
the host DSP and the W/
B input is logic high.
AD7859/AD7859L to ADSP-21xx
Figure 38 shows the AD7859/AD7859L interfaced to the
ADSP-21xx series of DSPs as a memory mapped device. A
single wait state may be necessary to interface the AD7859/
AD7859L to the ADSP-21xx depending on the clock speed of
the DSP. This wait state can be programmed via the Data
Memory Waitstate Control Register of the ADSP-21xx (please
see ADSP-2100 Family Users Manual for details). The following
instruction reads data from the AD7859/AD7859L:
MR = DM(ADC)
where ADC is the address of the AD7859/AD7859L.
ADSP-21xx*
CS
DB15–DB0
AD7859/
AD7859L*
*ADDITIONAL PINS OMITTED FOR CLARITY
D23–D8
ADDR
DECODE
DMS
DATA BUS
WR
RD
ADDRESS BUS
EN
WR
RD
IRQ2
A13–A0
BUSY
Figure 38. AD7859/AD7859L to ADSP-21xx Parallel
Interface
AD7859/AD7859L to TMS32020, TMS320C25 and TMS320C5x
Parallel interfaces between the AD7859/AD7859L and the
TMS32020, TMS320C25 and TMS320C5x family of DSPs are
shown in Figure 39. The memory mapped address chosen for
the AD7859/AD7859L should be chosen to fall in the I/O
memory space of the DSPs.
TMS32020/
TMS320C25/
TMS320C50*
CS
DB15–DB0
AD7859/
AD7859L*
*ADDITIONAL PINS OMITTED FOR CLARITY
D23–D0
ADDR
DECODE
DATA BUS
WR
RD
ADDRESS BUS
STRB
INTx
A15–A0
R/W
EN
IS
MSC
READY
TMS320C25
ONLY
BUSY
Figure 39. AD7859/AD7859L to TMS32020/C25/C5x Parallel
Interface
AD7859/AD7859L
REV. A
–26–
The parallel interface on the AD7859/AD7859L is fast enough
to interface to the TMS32020 with no extra wait states. If high
speed glue logic such as 74AS devices are used to drive the
WR
and
RD lines when interfacing to the TMS320C25, then again
no wait states are necessary. However, if slower logic is used,
data accesses may be slowed sufficiently when reading from and
writing to the part to require the insertion of one wait state. In
such a case, this wait state can be generated using the single OR
gate to combine the
CS and MSC signals to drive the READY
line of the TMS320C25, as shown in Figure 39. Extra wait
states will be necessary when using the TMS320C5x at their
fastest clock speeds. Wait states can be programmed via the
IOWSR and CWSR registers (please see TMS320C5x User
Guide for details).
Data is read from the ADC using the following instruction:
IN D,ADC
where D is the memory location where the data is to be stored
and ADC is the I/O address of the AD7859/AD7859L.
AD7859/AD7859L to TMS320C30
Figure 40 shows a parallel interface between the AD7859/
AD7859L and the TMS320C3x family of DSPs. The AD7859/
AD7859L is interfaced to the Expansion Bus of the TMS320C3x.
A single wait state is required in this interface. This can be pro-
grammed using the WTCNT bits of the Expansion Bus Control
register (see TMS320C3x Users Guide for details). Data from
the AD7859/AD7859L can be read using the following instruction:
LDI *ARn,Rx
where ARn is an auxiliary register containing the lower 16 bits
of the address of the AD7859/AD7859L in the TMS320C3x
memory space and Rx is the register into which the ADC data is
loaded.
TMS320C30*
CS
DB15–DB0
AD7859/
AD7859L*
*ADDITIONAL PINS OMITTED FOR CLARITY
XD23–XD0
ADDR
DECODE
EXPANSION DATA BUS
WR
RD
EXPANSION ADDRESS BUS
IOSTRB
INTx
XA12–XA0
XR/W
BUSY
Figure 40. AD7859/AD7859L to TMS320C30 Parallel Interface
AD7859/AD7859L to DSP5600x
Figure 41 shows a parallel interface between the AD7859/
AD7859L and the DSP5600x series of DSPs. The AD7859/
AD7859L should be mapped into the top 64 locations of Y data
memory. If extra wait states are needed in this interface, they
can be programmed using the Port A Bus Control Register
(please see DSP5600x Users Manual for details). Data can be
read from the AD7859/AD7859L using the following instruction:
MOVEO Y:ADC,X0
where ADC is the address in the DSP5600x address space
which the AD7859/AD7859L has been mapped to.
DSP56000/
DSP56002*
CS
DB15–DB0
AD7859/
AD7859L*
*ADDITIONAL PINS OMITTED FOR CLARITY
D23–D0
ADDR
DECODE
DS
DATA BUS
WR
RD
ADDRESS BUS
WR
RD
IRQ
A15–A0
X/Y
BUSY
Figure 41. AD7859/AD7859L to DSP5600x Parallel Interface
Interfacing the AD7859/AD7859L to an 8-Bit Data Bus
AD7859/AD7859L to 8051
This mode of operation allows the AD7859/AD7859L to be in-
terfaced directly to microcontrollors with an 8-bit data bus. The
AD7859/AD7859L is placed in byte mode by placing a logic
low signal on the W/
B pin.
Figure 42 shows a parallel interface between the AD7859/
AD7859L and the 8051 microcontroller. Here the W/
B pin is
tied logic low and the DB8/HBEN pin connected to line 1 of
Port 2. Port 0 serves as a multiplexed address/data bus to the
AD7859/AD7859L. Alternatively if the 8051 is not using exter-
nal memory or other memory mapped peripheral devices, line 2
of Port 2 (or any other line) could be used as the
CS signal.
8051*
ADDR
DECODE
CS
DB7–DB0
AD7859/
AD7859L*
*ADDITIONAL PINS OMITTED FOR CLARITY
WR
RD
WR
RD
INT0
P0
BUSY
LATCH
ALE
P2.1 DB8/HBEN
W/B
DGND
Figure 42. AD7859/AD7859L to 8051 Parallel Interface
APPLICATION HINTS
Grounding and Layout
The analog and digital supplies of the AD7859/AD7859L are
independent and separately pinned out to minimize coupling
between the analog and digital sections of the device. The part
has very good immunity to noise on the power supplies as can
be seen by the PSRR versus Frequency graph. However, care
should still be taken with regard to grounding and layout.
The printed circuit board on which the AD7859/AD7859L is
mounted should be designed such that the analog and digital
sections are separated and confined to certain areas of the
board. This facilitates the use of ground planes that can be eas-
ily separated. A minimum etch technique is generally best for
ground planes as it gives the best shielding. Digital and analog
ground planes should only be joined in one place. If the
AD7859/AD7859L is the only device requiring an AGND to
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

AD7859ASZ

Mfr. #:
Buy AD7859ASZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 8-Ch 12-Bit
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet