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SI5010-B-GMR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Rev. 1.4 6/08 Copyright © 2008 by Silicon Laboratories Si5010
Si5010
OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC
Features
Complete CDR solution includes the following:
Applications
Description
The Si5010 is a fully-integrated low-power clock and data recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-12/3 or STM-4/1 data
rates. DSPLL
®
technology eliminates sensitive noise entry points thus
making the PLL less susceptible to board-level interaction and helping to
ensure optimal jitter performance in the application.
The Si5010 represents an industry-leading combination of low-jitter,
low-power, and small size for high-speed CDRs. It operates from a single
2.5 V supply over the industrial temperature range (–40 to 85 °C).
Functional Block Diagram
Supports OC-12/3, STM-4/1
Low power, 293 mW (TYP OC-12)
Small footprint: 4x4 mm
DSPLL™ eliminates external loop
filter components
3.3 V tolerant control inputs
Exceeds All SONET/SDH jitter
specifications
Jitter generation
1.6 mUI
rms
(typ)
Device powerdown
Loss-of-lock indicator
Single 2.5 V supply
SONET/SDH/ATM routers
Add/drop multiplexers
Digital cross connects
Board level serial links
SONET/SDH test equipment
Optical transceiver modules
SONET/SDH regenerators
DSPLL
TM
Phase-Locked
Loop
Retimer
BUF
BUF
BUF
DIN+
DIN–
REXT
LOL
2
REFCLK+
REFCLK–
RATESEL
2
DOUT+
DOUT–
CLKOUT+
CLKOUT–
PWRDN/CAL
2
2
Bias
Ordering Information:
See page 16.
Pin Assignments
Si5010
GND
Pad
Connection
15
14
13
12
11
PWRDN/CAL
DOUT+
VDD
DOUT–
VDD
1
2
3
4
5
VDD
GND
REFCLK–
REXT
REFCLK+
20 19 18 17 16
NC
RATESEL
CLKOUT–
CLKOUT+
GND
6 7 8 9 10
LOL
GND
DIN+
DIN–
VDD
Top View
Si5010
2 Rev. 1.4
Si5010
Rev. 1.4 3
TABLE OF CONTENTS
Section Page
1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.1. DSPLL® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.2. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.3. Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.4. Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.5. Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.6. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.7. Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.8. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5. Pin Descriptions: Si5010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
9. 4x4 mm 20L QFN Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

SI5010-B-GMR

Mfr. #:
Buy SI5010-B-GMR
Manufacturer:
Silicon Labs
Description:
IC CLOCK/DATA RECOVERY LP 20-QFN
Lifecycle:
New from this manufacturer.
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