Si5010
16 Rev. 1.4
6. Ordering Guide
7. Top Mark
Part Number Package Voltage Pb-Free Temperature
Si5010-X-GM 20-lead QFN 2.5 Yes –40 to 85 °C
Notes:
1. “X” denotes product revision.
2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel.
3. These devices use a NiPdAu pre-plated finish on the leads that is fully RoHS6 compliant while being
fully compatible with both leaded and lead-free card assembly processes.
Part Number Die Revision (R) Assembly Date (YWW)
Si5010-B-GM B Y = Last digit of current year
WW = Work week
Si5010
Rev. 1.4 17
8. Package Outline
Figure 11 illustrates the package details for the Si5010. Table 9 lists the values for the dimensions shown in the
illustration.
Figure 11. 20-pin Quad Flat No-Lead (QFN)
Table 9. Package Dimensions
Symbol Millimeters Symbol Millimeters
Min Nom Max Min Nom Max
A 0.80 0.85 0.90 E2 1.95 2.10 2.25
A1 0.00 0.02 0.05 L 0.50 0.60 0.70
b 0.18 0.25 0.30 θ 12°
c—0.60 aaa 0.10
D 4.00 BSC bbb 0.10
D2 1.95 2.10 2.25 ccc 0.08
e 0.50 BSC ddd 0.10
E 4.00 BSC eee 0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VGGD-1.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
Si5010
18 Rev. 1.4
9. 4x4 mm 20L QFN Recommended PCB Layout
Symbol Parameter Dimensions
Min Nom Max
A Pad Row/Column Width/Length 2.23 2.25 2.28
D Thermal Pad Width/Height 2.03 2.08 2.13
e Pad Pitch 0.50 BSC
G Pad Row/Column Separation 2.43 2.46 2.48
R Pad Radius 0.12 REF
X Pad Width 0.23 0.25 0.28
Y Pad Length 0.94 REF
Z Pad Row/Column Extents 4.26 4.28 4.31
Notes:
1. All dimensions listed are in millimeters (mm).
2. The perimeter pads are to be Non-Solder Mask Defined (NSMD). Solder mask openings should be designed to leave 60-75 mm
separation between solder mask and pad metal, all the way around the pad.
3. The center thermal pad is to be Solder Mask Defined (SMD).
4. Thermal/Ground vias placed in the center pad should be no less than 0.2 mm (8 mil) diameter and tented from the top to prevent
solder from flowing into the via hole.
5. The stencil aperture should match the pad size (1:1 ratio) for the perimeter pads. A 3x3 array of 0.5 mm square stencil openings, on a
0.65 mm pitch, should be used for the center thermal pad.
6. A stencil thickness of 5 mil is recommended. The stencil should be laser cut and electropolished, with trapezoidal walls to facilitate
paste release.
7. A “No-Clean”, Type 3 solder paste should be used for assembly. Nitrogen purge during reflow is recommended.
8. Do not place any signal or power plane vias in these “keep out” regions.
9. Suggest four 0.38 mm (15 mil) vias to the ground plane.
See Note 8
Gnd Pin
Gnd Pin
Gnd Pin
See Note 9

SI5010-B-GMR

Mfr. #:
Manufacturer:
Silicon Labs
Description:
IC CLOCK/DATA RECOVERY LP 20-QFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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