Si5010
Rev. 1.4 7
Table 3. AC Characteristics (Clock & Data)
(V
A
2.5 V ±5%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Output Clock Rate f
CLK
150 — 666 MHz
Output Rise/Fall Time
(differential) t
R,
t
F
Figure 3 — 80 110 ps
Clock to Data Delay
OC-12
OC-3
t
(c-d)
Figure 2
835
4040
880
4090
930
4140
ps
ps
Input Return Loss 100 kHz–1 GHz — 20 — dB
Table 4. AC Characteristics (PLL Characteristics)
(V
DD
=2.5V ±5%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Jitter Tolerance (OC-12 Mode)
*
J
TOL(PP)
f = 30 Hz 40 — — UI
PP
f = 300 Hz 4 — — UI
PP
f=25 kHz 4 — — UI
PP
f = 250 kHz 0.4 — — UI
PP
Jitter Tolerance (OC-3 Mode)
*
J
TOL(PP)
f = 30 Hz 40 — — UI
PP
f = 300 Hz 4 — — UI
PP
f = 6.5 kHz 4 — — UI
PP
f=65 kHz 0.4 — — UI
PP
RMS Jitter Generation
*
J
GEN(rms)
with no jitter on serial data — 1.6 3.0 mUI
Peak-to-Peak Jitter Generation J
GEN(PP)
with no jitter on serial data — 25 55 mUI
Jitter Transfer Bandwidth
*
J
BW
OC-12 Mode — — 500 kHz
OC-3 Mode — — 130 kHz
Jitter Transfer Peaking
*
J
P
f < 2 MHz — .03 0.1 dB
Acquisition Time T
AQ
After falling edge of
PWRDN/CAL
1.45 1.5 1.7 ms
From the return of valid
data
40 60 150 μs
Input Reference Clock Duty Cycle C
DUTY
40 50 60 %
Reference Clock Range 19.44 155.52 MHz
Input Reference Clock Frequency
Tolerance
C
TOL
–100 — 100 ppm
Frequency Difference at which
Receive PLL goes out of Lock
(REFCLK compared to the divided
down VCO clock)
LOL 450 600 750 ppm
Frequency Difference at which
Receive PLL goes into Lock
(REFCLK compared to the divided
down VCO clock)
LOCK 150 300 450 ppm
*Note: Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 2
23
–1 data pattern.
