Si5010
10 Rev. 1.4
4. Functional Description
The Si5010 utilizes a phase-locked loop (PLL) to
recover a clock synchronous to the input data stream.
This clock is used to retime the data, and both the
recovered clock and data are output synchronously via
current mode logic (CML) drivers. Optimal jitter
performance is obtained by using Silicon Laboratories'
DSPLL
®
technology to eliminate the noise entry points
caused by external PLL filter components.
4.1. DSPLL
®
The PLL structure (shown in "3. Typical Application
Schematic" on page 9) utilizes Silicon Laboratories'
DSPLL technology to eliminate the need for external
loop filter components found in traditional PLL
implementations. This is achieved by using a digital
signal processing (DSP) algorithm to replace the loop
filter commonly found in analog PLL designs. This
algorithm processes the phase detector error term and
generates a digital control value to adjust the frequency
of the voltage-controlled oscillator (VCO). Because
external loop filter components are not required,
sensitive noise entry points are eliminated, thus making
the DSPLL less susceptible to board-level noise
sources that make SONET/SDH jitter compliance
difficult to attain.
4.2. PLL Self-Calibration
The Si5020 achieves optimal jitter performance by
using self-calibration circuitry to set the loop gain
parameters within the DSPLL. For the self-calibration
circuitry to operate correctly, the power supply voltage
must exceed 2.25 V when calibration occurs. For best
performance, the user should force a self-calibration
once the supply has stabilized on power-up.
A self-calibration can be initiated by forcing a
high-to-low transition on the power-down control input,
PWRDN/CAL, while a valid reference clock is supplied
to the REFCLK input. The PWRDN/CAL input should be
held high at least 1 μs before transitioning low to
guarantee a self-calibration. Several application circuits
that could be used to initiate a power-on self-calibration
are provided in Silicon Laboratories application note
“AN42: Controlling DSPLL Self-Calibration for the
Si5020/5018/5010 CDR Devices and Si531x Clock
Multiplier/Regenerator Devices”.
4.3. Multi-Rate Operation
The Si5010 supports clock and data recovery for
OC-12/3 and STM-4/1 data streams.
Multi-rate operation is achieved by configuring the
device to divide down the output of the VCO to the
desired data rate. The RATESEL configuration and
associated data rates are given in Table 7.
4.4. Reference Clock Detect
The Si5010 CDR requires an external reference clock
applied to the REFCLK input for normal device
operation. When REFCLK is absent, the LOL alarm will
always be asserted when it has been determined that
no activity exists on REFCLK, indicating the lock status
of the PLL is unknown. Additionally, the Si5010 uses the
reference clock to center the VCO operating frequency
so that clock and data can be recovered from the input
data stream. The VCO operates at an integer multiple of
the REFCLK frequency. (See “Lock Detect” section.)
The device will self configure for operation with one of
three reference clock frequencies. This eliminates the
need to externally configure the device to operate with a
particular reference clock. The REFCLK frequency
should be 19.44 MHz, 77.76 MHz, or 155.52 MHz with a
frequency accuracy of ±100 ppm.
4.5. Lock Detect
The Si5010 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. The circuit compares the frequency of a
divided-down version of the recovered clock with the
frequency of the applied reference clock (REFCLK). If
the recovered clock frequency deviates from that of the
reference clock by the amount specified in Table 4 on
page 7, the PLL is declared out-of-lock, and the
loss-of-lock (LOL) pin is asserted high. In this state, the
PLL will periodically try to reacquire lock with the
incoming data stream. During reacquisition, the
recovered clock may drift over a ±600 ppm range
relative to the applied reference clock, and the LOL
output alarm may toggle until the PLL has reacquired
frequency lock. Due to the low noise and stability of the
DSPLL, under the condition where data is removed from
the inputs, there is the possibility that the PLL will not
drift enough to render an out-of-lock condition.
If REFCLK is removed, the LOL output alarm will always
be asserted when it has been determined that no
activity exists on REFCLK, indicating the frequency lock
status of the PLL is unknown.
Note: LOL is not asserted during PWRDN/CAL.
Table 7. Data-Rate Configuration
RATESEL SONET/SDH
0 622.08 Mbps
1 155.52 Mbps
