Si5010
4 Rev. 1.4
1. Detailed Block Diagram
PWRDN/CAL
Calibration
DIN+
DIN–
CLKOUT+
CLKOUT–
DOUT+
DOUT–
LOL
REFCLK+
REFCLK–
RATESEL
Retime
Bias
Generation
REXT
DIN+
REFCLK+
RetimeRetime
Bias
Generation
Bias
Generation
Phase
Detector
Phase
Detector
Phase
Detector
A/D
DSP
VCO
CLK
Divider
n
Lock
Detector
c
c
Si5010
Rev. 1.4 5
2. Electrical Specifications
Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
Figure 2. Differential Clock to Data Timing
Figure 3. Differential DOUT and CLKOUT Rise/Fall Times
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition
Min
1
Typ
Max
1
Unit
Ambient Temperature T
A
–40 25 85 °C
Si5010 Supply Voltage
2
V
DD
2.375 2.5 2.625 V
Notes:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2. The Si5010 specifications are guaranteed when using the recommended application circuit (including component
tolerance) shown in "3. Typical Application Schematic" on page 9.
V
IS
V
ID
,V
OD
Differential
I/Os
Differential
Voltage Swing
Differential Peak-to-Peak Voltage
SIGNAL +
SIGNAL –
(SIGNAL+) – (SIGNAL–)
V
ICM
, V
OCM
V
t
Single Ended Voltage
DOUT
t
C-D
CLKOUT
DOUT,
CLKOUT
t
F
t
R
80%
20%
Si5010
6 Rev. 1.4
Table 2. DC Characteristics
(V
DD
=2.5V ±5%, T
A
= –40°C to 85°C)
Parameter Symbol Test Condition Min Typ Max Unit
Supply Current
OC-12
OC-3
I
DD
117
124
131
138
mA
Power Dissipation
OC-12
OC-3
P
D
293
310
344
362
mW
Common Mode Input Voltage
(DIN, REFCLK) V
ICM
varies with V
DD
—.80xV
DD
—V
Single Ended Input Voltage
(DIN, REFCLK) V
IS
See Figure 1 200 750 mV
PP
Differential Input Voltage Swing*
(DIN, REFCLK)
V
ID
See Figure 1 200 1500 mV
PP
Input Impedance (DIN, REFCLK) R
IN
Line-to-Line 84 100 116 Ω
Differential Output Voltage Swing
(DOUT)
V
OD
100 Ω Load
Line-to-Line
780 970 1260 mV
PP
Differential Output Voltage Swing
(CLKOUT)
V
OD
100 Ω Load
Line-to-Line
780 970 1260 mV
PP
Output Common Mode Voltage
(DOUT,CLKOUT)
V
OCM
100 Ω Load
Line-to-Line
—V
DD
0.23
—V
Output Impedance (DOUT,CLKOUT) R
OUT
Single-ended 84 100 116 Ω
Output Short to GND (DOUT,CLKOUT) I
SC(–)
—2531mA
Output Short to V
DD
(DOUT,CLKOUT) I
SC(+)
–17.5 –14.5 mA
Input Voltage Low (LVTTL Inputs) V
IL
—— .8V
Input Voltage High (LVTTL Inputs) V
IH
2.0 — V
Input Low Current (LVTTL Inputs) I
IL
——10μA
Input High Current (LVTTL Inputs) I
IH
——10μA
Output Voltage Low (LVTTL Outputs) V
OL
I
O
=2mA 0.4 V
Output Voltage High (LVTTL Outputs) V
OH
I
O
=2mA 2.0 V
Input Impedance (LVTTL Inputs) R
IN
10 kΩ
PWRDN/CAL Leakage Current I
PWRDN
V
PWRDN
0.8 V 15 25 35 μA
*Note: The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage
swing of the signal applied to the active input must exceed the specified minimum differential input voltage swing (V
ID
min) and the unused input must be ac-coupled to ground. When driving differentially, the difference between the positive
and negative input signals must exceed V
ID
min. (Each individual input signal needs to swing only half of this range.) In
either case, the voltage applied to any individual pin (DIN+, DIN–, REFCLK+, or REFCLK–) must not exceed the
specified maximum Input Voltage Range (V
IS
max).

SI5010-B-GMR

Mfr. #:
Manufacturer:
Silicon Labs
Description:
IC CLOCK/DATA RECOVERY LP 20-QFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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