Si5010
Rev. 1.4 15
12
13
DOUT–
DOUT+
OCML
Differential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN. It is
phase aligned with CLKOUT and is updated on the
rising edge of CLKOUT.
15 PWRDN/CAL I LVTTL
Powerdown.
To shut down the high-speed outputs and reduce
power consumption, hold this pin high. For normal
operation, hold this pin low.
Calibration.
To initiate an internal self-calibration, force a
high-to-low transition on this pin. (See "4.2. PLL
Self-Calibration" on page 10.)
Note: This input has a weak internal pulldown.
16
17
CLKOUT–
CLKOUT+
OCML
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN. In the absence of data, the output
clock is derived from REFCLK.
19 RATESEL I LVTTL
Data Rate Select.
This pin configures the onboard PLL for clock and
data recovery at one of two user selectable data
rates. See Table 7 for configuration settings.
Note: This input has a weak internal pulldown.
20 NC
No Connect.
This pin should be tied to ground.
Table 8. Si5010 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Level Description
