Figure 4. RESET and EN_OUT_ During Power-Up, EN_OUT_ Is
in Push-Pull Active-High Configuration
Sequencing
Each EN_OUT_ has one or more associated MON_
inputs, facilitating the voltage monitoring of multiple
power supplies. To sequence a system of power sup-
plies safely, the output voltage of a power supply must
be good before the next power supply may turn on.
Connect EN_OUT_ outputs to the enable input of an
external power supply and connect MON_ inputs to the
output of the power supply for voltage monitoring. More
than one MON_ may be used if the power supply has
multiple outputs.
Sequence Order
The MAX16047/MAX16049 utilize a system of ordered
slots to sequence multiple power supplies. To deter-
mine the sequence order, assign each EN_OUT_ to a
slot ranging from Slot 0 to Slot 11. EN_OUT_(s)
assigned to Slot 0 are turned on first, followed by out-
puts assigned to Slot 1, and so on through Slot 11.
Multiple EN_OUT_s assigned to the same slot turn on at
the same time.
Each slot has a built-in configurable sequence delay
(registers r50h to r54h) ranging from 20µs to 1.6s. During
a reverse sequence, slots are turned off in reverse order
starting from Slot 11. The MAX16047/MAX16049 may be
configured to power-down in simultaneous mode or in
reverse sequence mode as set in r54h[4]. See Tables 9,
10, and 11 for the EN_OUT_ slot assignment bits, and
Tables 12 and 13 for the sequence delays.
Monitoring Inputs While Sequencing
An enabled MON_ input may be assigned to a slot rang-
ing from Slot 1 to Slot 12. Monitoring inputs are always
checked at the beginning of a slot. The inputs are given
the power-up fault delay within which they must satisfy
the programmed undervoltage limit; otherwise a fault
condition will occur. The fault occurs regardless of the
critical fault enable bits. This undervoltage limit cannot
be disabled during power-up and power-down.
EN_OUT_s configured for open-drain, push-pull, or
charge-pump operation are always asserted at the end
of a slot, following the sequence delay. See Tables 9,
10, and 11 for the MON_ slot assignment bits.
Slot 0 does not monitor any MON_ input. Instead, Slot 0
waits for the Software Enable bit r4Dh[0] to be a logic ‘0’
and for the voltage on EN to rise above 0.525V before
asserting any assigned outputs. Outputs assigned to
Slot 0 are asserted before the Slot 0 sequence delay.
Generally, Slot 0 controls the enable inputs of power
supplies that are first in the sequence.
Similarly, Slot 12 does not control any EN_OUT_ out-
puts. Rather, Slot 12 monitors assigned MON_ inputs
and then enters the power-on state. Generally, Slot 12
monitors the last power supplies in the sequence. The
power-up sequence is complete when any MON_ inputs
assigned to Slot 12 exceed their undervoltage thresh-
olds and the sequence delay is expired. If no MON_
inputs are assigned to Slot 12, the power-up sequence
is complete after the slot sequence delay is expired.
The output rail(s) of a power supply should be moni-
tored by one or more MON_ inputs placed in the suc-
ceeding slot, ensuring that the output of the supply is
not checked until it has first been turned on. For exam-
ple, if a power supply uses EN_OUT1 located in Slot 3
and has two monitoring inputs, MON1 and MON2, they
must both be assigned to Slot 4. In this example,
EN_OUT1 turns on at the end of Slot 3. At the start of
Slot 4, MON1 and MON2 must exceed the undervolt-
age threshold before the programmed power-up fault
delay; otherwise a fault triggers.
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
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