MAX16047/MAX16049
Table 12. Sequence Delays and Fault Recovery (continued)
REGISTER/
EEPROM
ADDRESS
BIT RANGE DESCRIPTION
[2:0] Slot 0 Sequence Delay
[5:3] Slot 1 Sequence Delay50h
[7:6] Slot 2 Sequence Delay (LSBs)
[0] Slot 2 Sequence Delay (MSB)—see r50h[7:6]
[3:1] Slot 3 Sequence Delay
[6:4] Slot 4 Sequence Delay
51h
[7] Slot 5 Sequence Delay (LSB)—see r52h[1:0]
[1:0] Slot 5 Sequence Delay
[4:2] Slot 6 Sequence Delay52h
[7:5] Slot 7 Sequence Delay
[2:0] Slot 8 Sequence Delay
[5:3] Slot 9 Sequence Delay
53h
[7:6] Slot 10 Sequence Delay (LSBs)
[0] Slot 10 Sequence Delay (MSB)—see r53h[7:6]
[3:1] Slot 11 Sequence Delay
[4]
Reverse Sequence
0 = Power down all EN_OUT_s at the same time (simultaneously)
1 = Controlled power-down will be reverse of power-up sequence
54h
[7:5] Not used
Table 13. Slot Sequence Delay Selection
CONFIGURATION BITS SLOT SEQUENCE DELAY
000 20µs
001 12.5ms
010 25ms
011 50ms
100 100ms
101 200ms
110 400ms
111 1.6s
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
______________________________________________________________________________________ 31
MAX16047/MAX16049
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
32 ______________________________________________________________________________________
Closed-Loop Tracking
The MAX16047/MAX16049 track up to four voltages
during any time slot except Slot 0 and Slot 12.
Configure GPIO1–GPIO4 as sense line inputs (INS_) to
monitor tracking voltages. Configure GPIO6 as
FAULTPU to indicate tracking faults, if desired. See the
General-Purpose Inputs/Outputs
section for information
on configuring GPIOs.
For closed-loop tracking, use MON1, EN_OUT1, and
INS1 together to form a complete channel. Use MON2,
EN_OUT2, and INS2 to form a second complete chan-
nel. Use MON3, EN_OUT3, and INS3 together to form a
third channel; and use MON4, EN_OUT4, and INS4 to
form a fourth channel.
When configured for closed-loop tracking, assign each
EN_OUT_ to the same slot as its associated single
monitoring input (MON_). For example, if EN_OUT2 is
assigned to Slot 3, the monitoring input is MON2 and
must be assigned to Slot 3. This is because the MON_
input, checked at the start of the slot, must be valid
before tracking can begin. Tracking begins immediate-
ly and must finish before the power-up fault timeout
expires, or a fault will trigger. EN_OUT_ configured for
closed-loop tracking cannot be assigned to Slot 0.
The tracking control circuitry includes a ramp generator
and a comparator control block for each tracked volt-
age (see the
Functional Diagram
and Figure 5). The
comparator control block compares each INS_ voltage
with a control voltage ramp. If INS_ voltages vary from
the control ramp by more than 150mV (typ), the com-
parator control block signals an alert that dynamically
stops the ramp until the slow INS_ voltage rises to with-
in the allowed voltage window. The total tracking time is
extended under these conditions, but must still com-
plete within the selected power-up/power-down fault
timeout. The power-up/power-down tracking fault time-
out period is adjustable through r4Eh[3:0].
A voltage difference between any two tracking INS_
voltages exceeding 330mV generates a tracking fault,
forcing all EN_OUT_ voltages low and generating a
fault log. If configured as FAULTPU, GPIO6 asserts
when a tracking fault occurs.
The comparator control blocks also monitor INS_ volt-
ages with respect to input (MON_) voltages. Under nor-
mal conditions each INS_ tracks the control ramp until
the INS_ voltages reach the configured power-good
(PG) thresholds, set as a programmable percentage of
the MON_ voltage. Use register r64h to set the PG
thresholds (Table 14). Once PG is detected, the exter-
nal n-channel FET saturates with 5V (typ) applied
between gate and source. The slew rate for the control
ramp is programmable from 100V/s to 800V/s in
r4Fh[5:4] (see Table 12).
Power-down initiates when EN is forced low or when
the Software Enable bit in r4Dh[0] is set to ‘1.’ If the
Reverse Sequence bit is set (r54h[4]) INS_ voltages fol-
low a falling reference ramp to ground as long as
MON_ voltages remain high enough to supply the
required voltage/current. If a monitored voltage drops
faster than the control ramp voltage or the correspond-
ing MON_ voltage falls too quickly, power-down track-
ing operation is terminated and all EN_OUT_ voltages
are immediately forced to ground. If the Reverse
Sequence bit is set to ‘0,’ all EN_OUT_ voltages are
forced low simultaneously.
MON_
EN_OUT_ INS_
V
IN
V
OUT
REFERENCE
RAMP
LOGIC
ADC MUX
V
TH_PG
100Ω
GATE
DRIVE
Figure 5. Closed-Loop Tracking
MAX16047/MAX16049
Table 14. Power-Good (PG) Thresholds
REGISTER/
EEPROM
ADDRESS
BIT RANGE DESCRIPTION
[1:0]
00 = PG is asserted when monitored V
MON1
is 95% of V
INS1
01 = PG is asserted when monitored V
MON1
is 92.5% of V
INS1
10 = PG is asserted when monitored V
MON1
is 90% of V
INS1
11 = PG is asserted when monitored V
MON1
is 87.5% of V
INS1
[3:2]
00 = PG is asserted when monitored V
MON2
is 95% of V
INS2
01 = PG is asserted when monitored V
MON2
is 92.5% of V
INS2
10 = PG is asserted when monitored V
MON2
is 90% of V
INS2
11 = PG is asserted when monitored V
MON2
is 87.5% of V
INS2
[5:4]
00 = PG is asserted when monitored V
MON3
is 95% of V
INS3
01 = PG is asserted when monitored V
MON3
is 92.5% of V
INS3
10 = PG is asserted when monitored V
MON3
is 90% of V
INS3
11 = PG is asserted when monitored V
MON3
is 87.5% of V
INS3
64h
[7:6]
00 = PG is asserted when monitored V
MON4
is 95% of V
INS4
01 = PG is asserted when monitored V
MON4
is 92.5% of V
INS4
10 = PG is asserted when monitored V
MON4
is 90% of V
INS4
11 = PG is asserted when monitored V
MON4
is 87.5% of V
INS4
The MAX16047/MAX16049 include selectable internal
100Ω pulldown resistors to ensure that tracked voltages
are not held high by large external capacitors during a
fault event. The pulldowns help to ensure that monitored
INS_ voltages are fully discharged before the next
power-up cycle is initiated. These pulldowns are high
impedance during normal operation. Set r4Eh[7:4] to ‘1’
to enable the pulldown resistors (Table 12). These pull-
down resistors may also be used with EN_OUT1–
EN_OUT4 channels not configured for closed-loop track-
ing, which is useful to discharge the output capacitors of
a DC-DC converter during shutdown. For this case, con-
figure the GPIO as an INS_ input and set the 100Ω pull-
down bit, but do not enable closed-loop tracking.
Connect the INS_ input to the output of the power supply.
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
______________________________________________________________________________________ 33

MAX16047ETN+T

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Supervisory Circuits 12Ch EEPROM Prob System Manage
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