MAX16047/MAX16049
JTAG Serial Interface
The MAX16047/MAX16049 contain a JTAG port that
complies with a subset of the IEEE
®
1149.1 specifica-
tion. Either the I
2
C or the JTAG interface may be used
to access internal memory; however, only one interface
is allowed to run at a time. The MAX16047/MAX16049
do not support IEEE 1149.1 boundary-scan functionali-
ty. The MAX16047/MAX16049 contain extra JTAG
instructions and registers not included in the JTAG
specification that provide access to internal memory.
The extra instructions include LOAD ADDRESS, WRITE
DATA, READ DATA, REBOOT, SAVE, and USERCODE.
TEST ACCESS PORT
(TAP) CONTROLLER
INSTRUCTION REGISTER
[LENGTH = 5 BITS]
BYPASS REGISTER
[LENGTH = 1 BIT]
IDENTIFICATION REGISTER
[LENGTH = 32 BITS]
USER CODE REGISTER
[LENGTH = 32 BITS]
MEMORY ADDRESS REGISTER
[LENGTH = 8 BITS]
MEMORY READ REGISTER
[LENGTH = 8 BITS]
MEMORY WRITE REGISTER
[LENGTH = 8 BITS]
11111
00000
00011
00100
00101
00110
00111
MUX 2
TDO
TDI
TMS
TCK
01000
REGISTERS
AND EEPROM
01001
01010
01011
01100
MUX 1
00111
01000
01001
01010
01011
01100
REBOOT
SAVE
SETEXTRAM
SETEEPADD
RSTEXTRAM
RSTEEPADD
COMMAND
DECODER
R
PU
V
DB
Figure 13. JTAG Block Diagram
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
______________________________________________________________________________________ 49
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and Electronics Engineers, Inc.
MAX16047/MAX16049
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
50 ______________________________________________________________________________________
Test Access Port (TAP)
Controller State Machine
The TAP controller is a finite state machine that
responds to the logic level at TMS on the rising edge of
TCK. See Figure 14 for a diagram of the finite state
machine. The possible states are described below:
Test-Logic-Reset: At power-up, the TAP controller is in
the test-logic-reset state. The instruction register con-
tains the IDCODE instruction. All system logic of the
device operates normally. This state can be reached
from any state by driving TMS high for five clock cycles.
Run-Test/Idle: The run-test/idle state is used between
scan operations or during specific tests. The instruction
register and test data registers remain idle.
Select-DR-Scan: All test data registers retain their pre-
vious state. With TMS low, a rising edge of TCK moves
the controller into the capture-DR state and initiates a
scan sequence. TMS high during a rising edge on TCK
moves the controller to the select-IR-scan state.
Capture-DR: Data can be parallel-loaded into the test
data registers selected by the current instruction. If the
instruction does not call for a parallel load or the select-
ed test data register does not allow parallel loads, the
test data register remains at its current value. On the
rising edge of TCK, the controller goes to the shift-DR
state if TMS is low or it goes to the exit1-DR state if TMS
is high.
TEST-LOGIC-RESET
1
1
11
0
0
RUN-TEST/IDLE
0
0
0
0
1
1
1
0
0
1
0
1
1
0
1
0
1
SELECT-DR-SCAN SELECT-IR-SCAN
CAPTURE-DR
CAPTURE-IR
SHIFT-DR SHIFT-IR
EXIT1-DR EXIT1-IR
PAUSE-DR PAUSE-IR
EXIT2-DR EXIT2-IR
UPDATE-DR
UPDATE-IR
0
0
0
0
1
1
0
1
1
Figure 14. TAP Controller State Diagram
MAX16047/MAX16049
Shift-DR: The test data register selected by the current
instruction connects between TDI and TDO and shifts
data one stage toward its serial output on each rising
edge of TCK while TMS is low. On the rising edge of TCK,
the controller goes to the exit1-DR state if TMS is high.
Exit1-DR: While in this state, a rising edge on TCK puts
the controller in the update-DR state. A rising edge on
TCK with TMS low puts the controller in the pause-DR
state.
Pause-DR: Shifting of the test data registers halts while
in this state. All test data registers retain their previous
state. The controller remains in this state while TMS is
low. A rising edge on TCK with TMS high puts the con-
troller in the exit2-DR state.
Exit2-DR: A rising edge on TCK with TMS high while in
this state puts the controller in the update-DR state. A ris-
ing edge on TCK with TMS low enters the shift-DR state.
Update-DR: A falling edge on TCK while in the update-
DR state latches the data from the shift register path of
the test data registers into a set of output latches. This
prevents changes at the parallel output because of
changes in the shift register. On the rising edge of TCK,
the controller goes to the run-test/idle state if TMS is
low or goes to the select-DR-scan state if TMS is high.
Select-IR-Scan: All test data registers retain their previ-
ous states. The instruction register remains unchanged
during this state. With TMS low, a rising edge on TCK
moves the controller into the capture-IR state. TMS high
during a rising edge on TCK puts the controller back
into the test-logic-reset state.
Capture-IR: Use the capture-IR state to load the shift
register in the instruction register with a fixed value.
This value is loaded on the rising edge of TCK. If TMS
is high on the rising edge of TCK, the controller enters
the exit1-IR state. If TMS is low on the rising edge of
TCK, the controller enters the shift-IR state.
Shift-IR: In this state, the shift register in the instruction
register connects between TDI and TDO and shifts
data one stage for every rising edge of TCK toward the
TDO serial output while TMS is low. The parallel outputs
of the instruction register as well as all test data regis-
ters remain at their previous states. A rising edge on
TCK with TMS high moves the controller to the exit1-IR
state. A rising edge on TCK with TMS low keeps the
controller in the shift-IR state while moving data one
stage through the instruction shift register.
Exit1-IR: A rising edge on TCK with TMS low puts the
controller in the pause-IR state. If TMS is high on the
rising edge of TCK, the controller enters the update-IR
state.
Pause-IR: Shifting of the instruction shift register halts
temporarily. With TMS high, a rising edge on TCK puts
the controller in the exit2-IR state. The controller
remains in the pause-IR state if TMS is low during a ris-
ing edge on TCK.
Exit2-IR: A rising edge on TCK with TMS high puts the
controller in the update-IR state. The controller loops
back to shift-IR if TMS is low during a rising edge of
TCK in this state.
Update-IR: The instruction code that has been shifted
into the instruction shift register latches to the parallel
outputs of the instruction register on the falling edge of
TCK as the controller enters this state. Once latched,
this instruction becomes the current instruction. A rising
edge on TCK with TMS low puts the controller in the
run-test/idle state. With TMS high, the controller enters
the select-DR-scan state.
Instruction Register
The instruction register contains a shift register as well
as a latched parallel output and is 5 bits in length. When
the TAP controller enters the shift-IR state, the instruc-
tion shift register connects between TDI and TDO. While
in the shift-IR state, a rising edge on TCK with TMS low
shifts the data one stage toward the serial output at
TDO. A rising edge on TCK in the exit1-IR state or the
exit2-IR state with TMS high moves the controller to the
update-IR state. The falling edge of that same TCK
latches the data in the instruction shift register to the
instruction register parallel output. Instructions support-
ed by the MAX16047/MAX16049 and the respective
operational binary codes are shown in Table 27.
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
______________________________________________________________________________________ 51

MAX16047ETN+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits 12Ch EEPROM Prob System Manage
Lifecycle:
New from this manufacturer.
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